From: Claudiu Beznea <claudiu.beznea@tuxon.dev>
To: Prabhakar <prabhakar.csengg@gmail.com>,
"Claudiu Beznea" <claudiu.beznea.uj@bp.renesas.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Philipp Zabel" <p.zabel@pengutronix.de>,
"Geert Uytterhoeven" <geert+renesas@glider.be>,
"Magnus Damm" <magnus.damm@gmail.com>,
"Wolfram Sang" <wsa+renesas@sang-engineering.com>
Cc: John Madieu <john.madieu.xa@bp.renesas.com>,
linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Biju Das <biju.das.jz@bp.renesas.com>,
Fabrizio Castro <fabrizio.castro.jz@renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH 2/5] dt-bindings: pci: renesas,r9a08g045-pcie: Add RZ/V2H(P) support
Date: Wed, 25 Mar 2026 12:07:06 +0200 [thread overview]
Message-ID: <e0e4085f-4a9d-4ae8-80b8-d798c8408d84@tuxon.dev> (raw)
In-Reply-To: <20260318124450.163471-3-prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi, Prabhakar,
On 3/18/26 14:44, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add support for the PCIe controller found on the RZ/V2H(P) SoC. The
> RZ/V2H(P) controller is similar to the RZ/G3E variant but includes
> additional registers and configuration bits for PCIe lane control, and
> supports multilink operation selectable between a single x4 port or two
> independent x2 ports.
>
> The RZ/V2H(P) SoC supports multilink operation, in which it provides
> two independent PCIe channels (channel 0 and channel 1). To correctly
> configure the multilink mode and per-channel PCIe settings in the SYS
> registers, make the "linux,pci-domain" and "num-lanes" properties
> mandatory for this SoC and restrict their values as per the SoC
> requirements.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> .../bindings/pci/renesas,r9a08g045-pcie.yaml | 22 +++++++++++++++++--
> 1 file changed, 20 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml
> index 858ec02e6d62..57807d0abd9a 100644
> --- a/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml
> @@ -14,7 +14,7 @@ description: |
> with PCIe Base Specification 4.0 and supports different link speeds
> depending on the SoC variant:
> - Gen2 (5 GT/s): RZ/G3S
> - - Gen3 (8 GT/s): RZ/G3E, RZ/V2N
> + - Gen3 (8 GT/s): RZ/G3E, RZ/V2H(P), RZ/V2N
>
> properties:
> compatible:
> @@ -22,6 +22,7 @@ properties:
> - enum:
> - renesas,r9a08g045-pcie # RZ/G3S
> - renesas,r9a09g047-pcie # RZ/G3E
> + - renesas,r9a09g057-pcie # RZ/V2H(P)
> - items:
> - const: renesas,r9a09g056-pcie # RZ/V2N
> - const: renesas,r9a09g047-pcie
> @@ -220,7 +221,9 @@ allOf:
> properties:
> compatible:
> contains:
> - const: renesas,r9a09g047-pcie
> + enum:
> + - renesas,r9a09g047-pcie
> + - renesas,r9a09g057-pcie
> then:
> properties:
> interrupts:
> @@ -236,6 +239,21 @@ allOf:
> reset-names:
> maxItems: 1
>
There are empty lines b/w the above if-then conditionals. To cope with that
maybe drop this one here as well.
Thank you,
Claudiu
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: renesas,r9a09g057-pcie
> + then:
> + properties:
> + linux,pci-domain:
> + enum: [0, 1]
> + num-lanes:
> + enum: [2, 4]
> + required:
> + - linux,pci-domain
> + - num-lanes
> +
> unevaluatedProperties: false
>
> examples:
next prev parent reply other threads:[~2026-03-25 10:07 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-18 12:44 [PATCH 0/5] Add PCIe support for RZ/V2N and RZ/V2H(P) SoCs Prabhakar
2026-03-18 12:44 ` [PATCH 1/5] dt-bindings: pci: renesas,r9a08g045-pcie: Add RZ/V2N support Prabhakar
2026-03-18 16:34 ` Bjorn Helgaas
2026-03-18 19:46 ` Lad, Prabhakar
2026-03-18 12:44 ` [PATCH 2/5] dt-bindings: pci: renesas,r9a08g045-pcie: Add RZ/V2H(P) support Prabhakar
2026-03-19 9:34 ` Krzysztof Kozlowski
2026-03-19 21:25 ` Lad, Prabhakar
2026-03-25 10:07 ` Claudiu Beznea [this message]
2026-03-18 12:44 ` [PATCH 3/5] PCI: rzg3s-host: Use shared reset controls for power domain resets Prabhakar
2026-03-18 16:30 ` Bjorn Helgaas
2026-03-18 19:48 ` Lad, Prabhakar
2026-03-18 12:44 ` [PATCH 4/5] PCI: rzg3s-host: Prepare System Controller handling for multiple PCIe channels Prabhakar
2026-03-25 10:19 ` Claudiu Beznea
2026-03-25 11:54 ` Lad, Prabhakar
2026-03-18 12:44 ` [PATCH 5/5] PCI: rzg3s-host: Add support for RZ/V2H(P) SoC Prabhakar
2026-03-25 10:18 ` Claudiu Beznea
2026-03-25 11:53 ` Lad, Prabhakar
2026-03-26 12:56 ` Claudiu Beznea
2026-04-08 18:54 ` Lad, Prabhakar
2026-04-30 15:26 ` Manivannan Sadhasivam
2026-05-01 11:13 ` Lad, Prabhakar
2026-05-01 14:42 ` Manivannan Sadhasivam
2026-05-04 9:05 ` Geert Uytterhoeven
2026-05-06 12:02 ` Manivannan Sadhasivam
2026-05-06 12:07 ` Geert Uytterhoeven
2026-05-06 13:12 ` Manivannan Sadhasivam
2026-05-06 16:56 ` Lad, Prabhakar
2026-05-05 9:49 ` Lad, Prabhakar
2026-05-04 9:13 ` Geert Uytterhoeven
2026-05-05 9:54 ` Lad, Prabhakar
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