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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: LeJuFMfOcNZ3ygaRJi1fX69HHhTf0Ln8 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTE0MDA5NyBTYWx0ZWRfX9EyCNf8C2+rv 8mJ12vdAv8v07VkDyN0gyZWG2y/QWn+5ltaR81YaXVFLHGivXVuKQ8x01ZbNl5lI9GXHbQn3qNn c7qXYy6hYfIsnJaOEJGftglAr+vOs31fIraqGgDD6AW5g5vhzPGQySkdATrp18L95s5G8jrG1eu Fza84ruZbN0I5iL/JUS2LSpewib6+xjCIUy4P3Ze+rACrU+Sp0AvJnkMqMDCFkeDTyEA/brA1ud KG29KZ9TD7sb2kQsEA7EbxatLu4j9vNUkylOw12VlwsNs/jfxQdcwi0fiiO+SY6/bgyC/KnQ/LA c3b+sk73DXXouFoGjc5zILclcY9JT2IrjdNkg7w3cEFcokDjNQSzHFA+9W6mBpVmd5qbXZqrPM2 752bF432xH88Z1R4hEjPv77Jj6cJCQ== X-Authority-Analysis: v=2.4 cv=MNdtWcZl c=1 sm=1 tr=0 ts=69171bde cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=UUXEStRZTiKyGgBwSCQbmw==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=gEfo2CItAAAA:8 a=UXIAUNObAAAA:8 a=EUspDBNiAAAA:8 a=VxizJ4rqJv6xgcLMcuIA:9 a=QEXdDO2ut3YA:10 a=bFq2RbqkfqsA:10 a=uG9DUKGECoFWVXl0Dc02:22 a=sptkURWiP4Gy88Gu7hUp:22 a=a1s67YnXd6TbAZZNj1wK:22 a=poXaRoVlC6wW9_mwW8W4:22 X-Proofpoint-ORIG-GUID: LeJuFMfOcNZ3ygaRJi1fX69HHhTf0Ln8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-14_03,2025-11-13_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 priorityscore=1501 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 adultscore=0 malwarescore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511140097 On 11/14/2025 5:30 PM, Akhil P Oommen wrote: > On 11/10/2025 1:21 PM, Krzysztof Kozlowski wrote: >> On Fri, Nov 07, 2025 at 02:20:08AM +0530, Akhil P Oommen wrote: >>> From: Jie Zhang >>> >>> RGMU a.k.a Reduced Graphics Management Unit is a small state machine >>> with the sole purpose of providing IFPC (Inter Frame Power Collapse) >>> support. Compared to GMU, it doesn't manage GPU clock, voltage >>> scaling, bw voting or any other functionalities. All it does is detect >>> an idle GPU and toggle the GDSC switch. As it doesn't access DDR space, >>> it doesn't require iommu. >>> >>> So far, only Adreno 612 GPU has an RGMU core. Document RGMU in the GMU's >>> schema. >>> >>> Signed-off-by: Jie Zhang >>> Signed-off-by: Akhil P Oommen >>> --- >>> .../devicetree/bindings/display/msm/rgmu.yaml | 131 +++++++++++++++++++++ >>> MAINTAINERS | 1 + >>> 2 files changed, 132 insertions(+) >>> >>> diff --git a/Documentation/devicetree/bindings/display/msm/rgmu.yaml b/Documentation/devicetree/bindings/display/msm/rgmu.yaml >>> new file mode 100644 >>> index 000000000000..7621556477d0 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/display/msm/rgmu.yaml >> >> Filename matching compatible, so qcom,adreno-rgmu.yaml >> >> >>> @@ -0,0 +1,131 @@ >>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >>> +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. >>> +%YAML 1.2 >>> +--- >>> + >>> +$id: http://devicetree.org/schemas/display/msm/rgmu.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: RGMU attached to certain Adreno GPUs >>> + >>> +maintainers: >>> + - Rob Clark >>> + >>> +description: | >> >> Do not need '|' unless you need to preserve formatting. >> >>> + RGMU (Reduced Graphics Management Unit) IP is present in some GPUs that >>> + belong to Adreno A6xx family. It is a small state machine that helps to >>> + toggle the GX GDSC (connected to CX rail) to implement IFPC feature and save >>> + power. >>> + >>> +properties: >>> + compatible: >>> + items: >>> + - const: qcom,adreno-rgmu-612.0 >>> + - const: qcom,adreno-rgmu >>> + >>> + reg: >>> + items: >>> + - description: Core RGMU registers >>> + >>> + reg-names: >>> + items: >>> + - const: gmu >> >> Drop reg-names, useless for one entry with same name as the block name. > > Just to confirm, drop only reg-names, but keep 'reg'? Wait. We should keep 'reg'. If we remove 'reg-names' here, we cannot use reg-names in DT too because we are setting additionalProperties to False, right? -Akhil. > > -Akhil > >> >>> + >>> + clocks: >>> + items: >>> + - description: GMU clock >>> + - description: GPU CX clock >>> + - description: GPU AXI clock >>> + - description: GPU MEMNOC clock >>> + - description: GPU SMMU vote clock >>> + >>> + clock-names: >>> + items: >>> + - const: gmu >>> + - const: cxo >>> + - const: axi >>> + - const: memnoc >>> + - const: smmu_vote >>> + >>> + power-domains: >>> + items: >>> + - description: CX GDSC power domain >>> + - description: GX GDSC power domain >>> + >>> + power-domain-names: >>> + items: >>> + - const: cx >>> + - const: gx >>> + >>> + interrupts: >>> + items: >>> + - description: GMU OOB interrupt >>> + - description: GMU interrupt >>> + >>> + interrupt-names: >>> + items: >>> + - const: oob >>> + - const: gmu >>> + >>> + operating-points-v2: true >>> + opp-table: >>> + type: object >>> + >>> +required: >> >> compatible >> >>> + - reg >>> + - reg-names >>> + - clocks >>> + - clock-names >>> + - power-domains >>> + - power-domain-names >>> + - interrupts >>> + - interrupt-names >> >> Keep the same order as in properties. >> >>> + - operating-points-v2 >>> + >>> +additionalProperties: false >>> + >>> +examples: >>> + - | >>> + #include >>> + #include >>> + #include >>> + #include >>> + >>> + rgmu: rgmu@506a000 { >> >> Drop label. >> >> Node names should be generic. See also an explanation and list of >> examples (not exhaustive) in DT specification: >> https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation >> If you cannot find a name matching your device, please check in kernel >> sources for similar cases or you can grow the spec (via pull request to >> DT spec repo). >> >> Best regards, >> Krzysztof >> >