From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753176AbdK1Mjb (ORCPT ); Tue, 28 Nov 2017 07:39:31 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:11034 "EHLO szxga05-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752729AbdK1Mj0 (ORCPT ); Tue, 28 Nov 2017 07:39:26 -0500 Subject: Re: [question] extract the feature bits width to 4 To: Suzuki K Poulose CC: "mark.rutland@arm.com" , Linux Kernel Mailing List , "linux-arm-kernel@lists.infradead.org" References: <17ab0a11-7ca2-ff22-35d6-7446dbccc3ea@huawei.com> From: gengdongjiu Message-ID: Date: Tue, 28 Nov 2017 20:38:39 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.3.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 8bit X-Originating-IP: [10.142.68.147] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090201.5A1D58D5.0021,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 34c06dfa94e845b56b05a38235458fc7 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2017/11/28 19:40, Suzuki K Poulose wrote: > Cc: linux-arm-kernel > > On 28/11/17 11:17, gengdongjiu wrote: >> Hi,suzuki/mark, > > Hello! > > Please Cc linux-arm-kernel mailing list in the future for any arm/arm64 kernel > related queries. Thanks a lot for the reply, Ok > >> >>    very sorry to disturb you, I have a question that want to consult with you. For the CPU feature detection, >> why we use extract 4 bits width for the feature match instead of the actual bits number[1]?  may be the actual hardware feature bit more than 4 bits. > > > There are features which could be more or less than 4bit wide. However, > all the arm64_cpu_capabilities features are 4bits and hence the hard coded > bits there. If we ever come across handling capabilities which are not > standard size, we could add the necessary code to support it. yes, normally the arm64_cpu_capabilities features are 4bits. However, in my platform, there is a private CPU feature which is more than 4bits. > > Are you planning to add something which does require the change ? Please > feel free to send patches. If I support this feature, I have to change it and not use 4bits. This CPU feature is private, I does not want to upstream the whole feature. If I only send the change about using actual width instead of 4 bits when detection feature , I am not sure you are agree. > > Cheers > > Suzuki > > >> thanks! >> >> static inline int __attribute_const__ >> cpuid_feature_extract_field(u64 features, int field, bool sign) >> { >>          return cpuid_feature_extract_field_width(features, field, 4, sign); >> } >> >> static bool >> feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) >> { >>          int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign); >> >>          return val >= entry->min_field_value; >> } >> >> > > > . >