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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae6e82dedc0sm1354487066b.160.2025.07.17.05.54.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 17 Jul 2025 05:54:19 -0700 (PDT) Message-ID: Date: Thu, 17 Jul 2025 14:54:17 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/3] media: qcom: camss: tpg: Add TPG support for SA8775P To: Wenmeng Liu , Robert Foss , Todor Tomov , Bryan O'Donoghue , Mauro Carvalho Chehab Cc: linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org References: <20250717-lemans_tpg-v2-0-a2538659349c@quicinc.com> <20250717-lemans_tpg-v2-3-a2538659349c@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250717-lemans_tpg-v2-3-a2538659349c@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzE3MDExMyBTYWx0ZWRfX83two4kKmpgF 4w9/g/mQBBgFAF4W7oLiICJ4dz7jT203pmLGKBcLGMONP1N+cjeyi4OfaqRykvBGI8f+L2RTcmA WeJKUdiBhvtqYqFp/AbVjbrhE/eZaRzIQnjLTX2t0R+fQClrmKjkPLzlJweMjhf/YN4J/3k7RiZ SwcyO2NFQcyZKCYX0CoG9WTGmGde8G/wKEiP+z92aF6ug44scfjMcMvBgBy4RlqMgAEzl9h25ou JjemFGKF633hxDmsvxDkq/GtFhVQFSnnab5nvaKidj57VV1oadpoGlxl0H7+Wy+PUz+j8BtxAb+ mP1Y+4KvwVH1czmG7wjBplBsWDKr8Iq1EdkdPK2dtITMvbFVXy+6kOXe9sF5KudBYBoLPE2OCjb 2EfQ+wGPWdjC62Z7x7wTtjzqKrfzPL4pNWAxjHJD7pdQU3zqtYyiUsvESh0LUa6Gj6zZtUXr X-Proofpoint-GUID: YKJOs2Ktck6jPS0BdTFTzF8-2HrFgScc X-Proofpoint-ORIG-GUID: YKJOs2Ktck6jPS0BdTFTzF8-2HrFgScc X-Authority-Analysis: v=2.4 cv=McZsu4/f c=1 sm=1 tr=0 ts=6878f27d cx=c_pps a=7E5Bxpl4vBhpaufnMqZlrw==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=COk6AnOGAAAA:8 a=pSl5WCw3oxHEiR9bIskA:9 a=QEXdDO2ut3YA:10 a=pJ04lnu7RYOZP9TFuWaZ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-17_01,2025-07-17_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxlogscore=999 impostorscore=0 mlxscore=0 phishscore=0 adultscore=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 suspectscore=0 spamscore=0 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507170113 On 7/17/25 5:20 AM, Wenmeng Liu wrote: > Add support for TPG found on SA8775P. > > Signed-off-by: Wenmeng Liu > --- [...] > +static int tpg_stream_on(struct tpg_device *tpg) > +{ > + struct tpg_testgen_config *tg = &tpg->testgen; > + struct v4l2_mbus_framefmt *input_format; > + const struct tpg_format_info *format; > + u8 lane_cnt = tpg->res->lane_cnt; > + u8 i; > + u8 dt_cnt = 0; > + u32 val; > + > + /* Loop through all enabled VCs and configure stream for each */ > + for (i = 0; i < tpg->res->vc_cnt; i++) { > + input_format = &tpg->fmt[MSM_TPG_PAD_SRC + i]; > + format = tpg_get_fmt_entry(tpg->res->formats->formats, > + tpg->res->formats->nformats, > + input_format->code); > + > + val = (input_format->height & 0xffff) << TPG_VC_m_DT_n_CFG_0_FRAME_HEIGHT; > + val |= (input_format->width & 0xffff) << TPG_VC_m_DT_n_CFG_0_FRAME_WIDTH; > + writel_relaxed(val, tpg->base + TPG_VC_m_DT_n_CFG_0(i, dt_cnt)); > + > + val = format->data_type << TPG_VC_m_DT_n_CFG_1_DATA_TYPE; > + writel_relaxed(val, tpg->base + TPG_VC_m_DT_n_CFG_1(i, dt_cnt)); > + > + val = (tg->mode - 1) << TPG_VC_m_DT_n_CFG_2_PAYLOAD_MODE; > + val |= 0xBE << TPG_VC_m_DT_n_CFG_2_USER_SPECIFIED_PAYLOAD; > + val |= format->encode_format << TPG_VC_m_DT_n_CFG_2_ENCODE_FORMAT; > + writel_relaxed(val, tpg->base + TPG_VC_m_DT_n_CFG_2(i, dt_cnt)); > + > + writel_relaxed(0xA00, tpg->base + TPG_VC_n_COLOR_BARS_CFG(i)); > + > + writel_relaxed(0x4701, tpg->base + TPG_VC_n_HBI_CFG(i)); > + writel_relaxed(0x438, tpg->base + TPG_VC_n_VBI_CFG(i)); Please provide context for the magic numbers> + > + writel_relaxed(0x12345678, tpg->base + TPG_VC_n_LSFR_SEED(i)); > + > + /* configure one DT, infinite frames */ > + val = i << TPG_VC_n_CFG0_VC_NUM; > + val |= 0 << TPG_VC_n_CFG0_NUM_FRAMES; > + writel_relaxed(val, tpg->base + TPG_VC_n_CFG0(i)); > + } > + > + writel_relaxed(1, tpg->base + TPG_TOP_IRQ_MASK); > + > + val = 1 << TPG_CTRL_TEST_EN; > + val |= 0 << TPG_CTRL_PHY_SEL; > + val |= (lane_cnt - 1) << TPG_CTRL_NUM_ACTIVE_LANES; > + val |= 0 << TPG_CTRL_VC_DT_PATTERN_ID; > + val |= (tpg->res->vc_cnt - 1) << TPG_CTRL_NUM_ACTIVE_VC; > + writel_relaxed(val, tpg->base + TPG_CTRL); You want the last writel here (and in _off()) to *not* be relaxed, so that all the prior accesses would have been sent off to the hw [...] > +static u32 tpg_hw_version(struct tpg_device *tpg) > +{ > + u32 hw_version; > + u32 hw_gen; > + u32 hw_rev; > + u32 hw_step; > + > + hw_version = readl_relaxed(tpg->base + TPG_HW_VERSION); > + hw_gen = (hw_version >> HW_VERSION_GENERATION) & 0xF; > + hw_rev = (hw_version >> HW_VERSION_REVISION) & 0xFFF; > + hw_step = (hw_version >> HW_VERSION_STEPPING) & 0xFFFF; FIELD_GET() > + dev_dbg(tpg->camss->dev, "tpg HW Version = %u.%u.%u\n", > + hw_gen, hw_rev, hw_step); dev_dbg_once() [...] > +static int tpg_reset(struct tpg_device *tpg) > +{ > + writel_relaxed(0, tpg->base + TPG_CTRL); > + writel_relaxed(0, tpg->base + TPG_TOP_IRQ_MASK); > + writel_relaxed(1, tpg->base + TPG_TOP_IRQ_CLEAR); > + writel_relaxed(1, tpg->base + TPG_IRQ_CMD); > + writel_relaxed(1, tpg->base + TPG_CLEAR); similar comment as before Konrad