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Mon, 13 Oct 2025 22:39:18 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGzNWsTvFSwkJcmErpReie+BnX+Tvcx5O8Z7ZWO1k+OYQIw6XA2734NpxW3Pui5uE9foskOWQ== X-Received: by 2002:a17:902:ce88:b0:26a:8171:daf7 with SMTP id d9443c01a7336-2902723f086mr388951955ad.16.1760420357620; Mon, 13 Oct 2025 22:39:17 -0700 (PDT) Received: from [10.218.42.132] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29034f4ae6csm151903735ad.108.2025.10.13.22.39.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 13 Oct 2025 22:39:17 -0700 (PDT) Message-ID: Date: Tue, 14 Oct 2025 11:09:08 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 1/4] arm64: dts: qcom: Add PCIe 5 support for HAMOA-IOT-SOM platform To: Ziyue Zhang , andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, jingoohan1@gmail.com, mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, bhelgaas@google.com, johan+linaro@kernel.org, vkoul@kernel.org, kishon@kernel.org, neil.armstrong@linaro.org, abel.vesa@linaro.org, kw@linux.com Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, qiang.yu@oss.qualcomm.com, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com References: <20250922075509.3288419-1-ziyue.zhang@oss.qualcomm.com> <20250922075509.3288419-2-ziyue.zhang@oss.qualcomm.com> Content-Language: en-US From: Krishna Chaitanya Chundru In-Reply-To: <20250922075509.3288419-2-ziyue.zhang@oss.qualcomm.com> Content-Type: text/plain; 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Add perst > wake and clkreq sideband signals and required regulators in PCIe5 > controller and PHY device tree node. > > Signed-off-by: Ziyue Zhang Reviewed-by: Krishna Chaitanya Chundru - Krishna Chaitanya. > --- > arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi | 40 +++++++++++++++++++++ > 1 file changed, 40 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi > index 1aead50b8920..0c8ae34c1f37 100644 > --- a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi > +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi > @@ -407,6 +407,23 @@ &pcie4_phy { > status = "okay"; > }; > > +&pcie5 { > + perst-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; > + wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; > + > + pinctrl-0 = <&pcie5_default>; > + pinctrl-names = "default"; > + > + status = "okay"; > +}; > + > +&pcie5_phy { > + vdda-phy-supply = <&vreg_l3i_0p8>; > + vdda-pll-supply = <&vreg_l3e_1p2>; > + > + status = "okay"; > +}; > + > &pcie6a { > perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; > wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; > @@ -477,6 +494,29 @@ wake-n-pins { > }; > }; > > + pcie5_default: pcie5-default-state { > + clkreq-n-pins { > + pins = "gpio150"; > + function = "pcie5_clk"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + perst-n-pins { > + pins = "gpio149"; > + function = "gpio"; > + drive-strength = <2>; > + bias-disable; > + }; > + > + wake-n-pins { > + pins = "gpio151"; > + function = "gpio"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + }; > + > pcie6a_default: pcie6a-default-state { > clkreq-n-pins { > pins = "gpio153";