From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 35D0733D4F8 for ; Fri, 3 Jul 2026 05:10:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783055426; cv=none; b=sv3Ay4L7r7NhaMZcLE5k3my66laaMS0UnYSgFfIeUwPGQBMLAJQHLhcsR3gFBKUKAHYBTn3JnWm4g2YEP6qYpSIZhr+nYfd2h/1MVJtU2BcokIH9mdpn3L1gLzECZoYZ2nnpVlbKRcMhPHmJENj4pXs9iYJGTumgBsLnEIre9Gg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783055426; c=relaxed/simple; bh=4XB1SQRtMhzH7Y3vbnI5tWzJG9PfjDjfBdugTPmYg30=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=IuKHgTewTgN4fa3U3ZbH2dKuIfbr25/4R0+H4mFfJ2vELHK0AAQgMpJ54W6gMcaGXy8xJCVYjKaM/gIhJwGGWeqN5qZWpECQF4F+A8hsYdvlQqKLK7ReX+oOrNRcPA0FqtpZnlCJe6f/VSKBjbF7B/NAx0fqwChsjR2olzXeckQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=vLi9+39+; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="vLi9+39+" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9725122D7; Thu, 2 Jul 2026 22:10:12 -0700 (PDT) Received: from [10.163.170.216] (unknown [10.163.170.216]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 85A543F673; Thu, 2 Jul 2026 22:10:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1783055417; bh=4XB1SQRtMhzH7Y3vbnI5tWzJG9PfjDjfBdugTPmYg30=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=vLi9+39+W6d95A7ed9v9SVPNWFu+YmilP+dpJ1XCIZNd50qCspynISZTpEWWZh0zk tMpUMDaVzZDfczo+1x+9eP+4620RfgfIhl5C2P5Bct9TZ16SWAzh303GNRolnKJnX1 PXzLUdq2x+yKevrJDcKLhE6JFGspvBEnGkLfQT4U= Message-ID: Date: Fri, 3 Jul 2026 10:40:11 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/5] arm64: cputype: Add C1-Nano definitions To: Linu Cherian , Catalin Marinas , Will Deacon , Ryan Roberts , Kevin Brodsky , Suzuki K Poulose , Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20260701094131.677636-1-linu.cherian@arm.com> <20260701094131.677636-5-linu.cherian@arm.com> Content-Language: en-US From: Anshuman Khandual In-Reply-To: <20260701094131.677636-5-linu.cherian@arm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 01/07/26 3:11 PM, Linu Cherian wrote: > Add cputype definitions for C1-Nano. > > The definition can be found in C1-Nano TRM, > https://developer.arm.com/documentation/107753/0002 > as part of MIDR_EL1 bit descriptions. > > This is going to be used in the bbml3 support list. > > Signed-off-by: Linu Cherian > --- > arch/arm64/include/asm/cputype.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h > index e41fae46426b..1fa29616e586 100644 > --- a/arch/arm64/include/asm/cputype.h > +++ b/arch/arm64/include/asm/cputype.h > @@ -100,6 +100,7 @@ > #define ARM_CPU_PART_CORTEX_A720AE 0xD89 > #define ARM_CPU_PART_C1_ULTRA 0xD8C > #define ARM_CPU_PART_NEOVERSE_N3 0xD8E > +#define ARM_CPU_PART_C1_NANO 0xD8A Part number checks out in the TRM. > #define ARM_CPU_PART_C1_PRO 0xD8B > #define ARM_CPU_PART_C1_PREMIUM 0xD90 > > @@ -195,6 +196,7 @@ > #define MIDR_CORTEX_A720AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720AE) > #define MIDR_C1_ULTRA MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_ULTRA) > #define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3) > +#define MIDR_C1_NANO MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_NANO) > #define MIDR_C1_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_PRO) > #define MIDR_C1_PREMIUM MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_PREMIUM) > #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) Reviewed-by: Anshuman Khandual