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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Arkadiusz Kubalewski , Michal Michalik , Vadim Fedorenko , Milena Olech , intel-wired-lan@lists.osuosl.org, linux-kernel@vger.kernel.org References: <20261110143119.2313907-1-poros@redhat.com> Content-Language: en-US From: Ivan Vecera In-Reply-To: <20261110143119.2313907-1-poros@redhat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 On 11/10/26 15:31, Petr Oros wrote: > The DPLL core checks only that a pin may change its state, which states > a pin accepts is left to the driver. The ice callbacks turn the > requested state into an enable flag by comparing it with the one state > that enables the pin, so every other state disables it, including the > one that has no meaning for the pin. > > The inputs of the EEC and PPS DPLLs are enabled by selectable, as these > DPLLs select their reference automatically. A request for connected, > which Documentation/driver-api/dpll.rst reserves for manual mode and > for pins with the state-connected-override capability, disables the > input. On an E810: > > # dpll pin set id 1 parent-device 0 state connected > # dpll pin show id 1 > ... state disconnected on both DPLLs > > A recovered clock pin is connected to or disconnected from its parent > pin, and a request for selectable disconnects it: > > # dpll pin set id 2109 parent-pin 2094 state selectable > # dpll pin show id 2109 > ... state disconnected on parent 2094 > > Add a helper that translates the state for a pin given the state that > enables it. Disconnected disables the pin and anything else is refused > with -EINVAL and an extack message. Use it for the input and recovered > clock pins, and for the output pins, which already refused selectable > and now tell the user why. > > The SMA pins have the same problem. It is left out here, as the rework > of the SMA and U.FL pin control that is queued for net-next refuses the > states these pins cannot serve. > > Found with the pin state selftest of the dpllsim series running against > an ice E810. ;-) good catch! > > Fixes: d7999f5ea64bb1 ("ice: implement dpll interface to control cgu") > Signed-off-by: Petr Oros Reviewed-by: Ivan Vecera