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Tue, 16 Aug 2022 04:57:34 -0700 (PDT) Received: from [192.168.255.10] ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id s13-20020aa78bcd000000b0052cdb06c125sm8295548pfd.159.2022.08.16.04.57.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 16 Aug 2022 04:57:34 -0700 (PDT) Message-ID: Date: Tue, 16 Aug 2022 19:57:22 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.12.0 Subject: Re: [PATCH v2 1/7] perf/x86/core: Update x86_pmu.pebs_capable for ICELAKE_{X,D} Content-Language: en-US To: Peter Zijlstra , Paolo Bonzini Cc: Sean Christopherson , Jim Mattson , linux-kernel@vger.kernel.org, kvm@vger.kernel.org, "Liang, Kan" References: <20220721103549.49543-1-likexu@tencent.com> <20220721103549.49543-2-likexu@tencent.com> <959fedce-aada-50e4-ce8d-a842d18439fa@redhat.com> <94e6c414-38e1-ebd7-0161-34548f0b5aae@gmail.com> <952632db-b090-ceb9-1467-a6b598ca2b02@linux.intel.com> From: Like Xu In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 15/8/2022 10:30 pm, Peter Zijlstra wrote: > On Mon, Aug 15, 2022 at 09:06:01AM -0400, Liang, Kan wrote: > >> Goldmont Plus should be the only platform which supports extended PEBS >> but doesn't have Baseline. > > Like so then... > > diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c > index 2db93498ff71..cb98a05ee743 100644 > --- a/arch/x86/events/intel/core.c > +++ b/arch/x86/events/intel/core.c > @@ -6291,10 +6291,8 @@ __init int intel_pmu_init(void) > x86_pmu.pebs_aliases = NULL; > x86_pmu.pebs_prec_dist = true; > x86_pmu.pebs_block = true; > - x86_pmu.pebs_capable = ~0ULL; > x86_pmu.flags |= PMU_FL_HAS_RSP_1; > x86_pmu.flags |= PMU_FL_NO_HT_SHARING; > - x86_pmu.flags |= PMU_FL_PEBS_ALL; > x86_pmu.flags |= PMU_FL_INSTR_LATENCY; > x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; > > @@ -6337,10 +6335,8 @@ __init int intel_pmu_init(void) > x86_pmu.pebs_aliases = NULL; > x86_pmu.pebs_prec_dist = true; > x86_pmu.pebs_block = true; > - x86_pmu.pebs_capable = ~0ULL; > x86_pmu.flags |= PMU_FL_HAS_RSP_1; > x86_pmu.flags |= PMU_FL_NO_HT_SHARING; > - x86_pmu.flags |= PMU_FL_PEBS_ALL; > x86_pmu.flags |= PMU_FL_INSTR_LATENCY; > x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; > x86_pmu.lbr_pt_coexist = true; > diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c > index ba60427caa6d..ac6dd4c96dbc 100644 > --- a/arch/x86/events/intel/ds.c > +++ b/arch/x86/events/intel/ds.c > @@ -2262,6 +2262,7 @@ void __init intel_ds_init(void) > PERF_SAMPLE_BRANCH_STACK | > PERF_SAMPLE_TIME; > x86_pmu.flags |= PMU_FL_PEBS_ALL; > + x86_pmu.pebs_capable = ~0ULL; > pebs_qual = "-baseline"; > x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_EXTENDED_REGS; > } else { Looks good to me. This diff touches PMU_FL_PEBS_ALL, which is less needed for guest PEBS fixes. It has be sent out separately to the linux-perf-users group for further review.