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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id x4-20020a2e9dc4000000b00295bbe17b46sm27496ljj.132.2023.04.19.18.11.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 19 Apr 2023 18:11:30 -0700 (PDT) Message-ID: Date: Thu, 20 Apr 2023 04:11:29 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.0 Subject: Re: [PATCH v2 14/17] drm/msm/dpu: Document and enable TEAR interrupts on DSI interfaces Content-Language: en-GB To: Marijn Suijten , Rob Clark , Abhinav Kumar , Sean Paul , David Airlie , Daniel Vetter , Adam Skladowski , Loic Poulain , Bjorn Andersson , Kuogee Hsieh , Robert Foss , Vinod Koul , Rajesh Yadav , Jeykumar Sankaran , Neil Armstrong , Chandan Uddaraju Cc: ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno , Konrad Dybcio , Martin Botka , Jami Kettunen , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jordan Crouse , Archit Taneja , Sravanthi Kollukuduru References: <20230411-dpu-intf-te-v2-0-ef76c877eb97@somainline.org> <20230411-dpu-intf-te-v2-14-ef76c877eb97@somainline.org> From: Dmitry Baryshkov In-Reply-To: <20230411-dpu-intf-te-v2-14-ef76c877eb97@somainline.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 17/04/2023 23:21, Marijn Suijten wrote: > All SoCs since DPU 5.0.0 have the tear interrupt registers moved out of > the PINGPONG block and into the INTF block. Wire up these interrupts > and IRQ masks on all supported hardware. > > Signed-off-by: Marijn Suijten > --- > .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 12 ++++++---- > .../drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 12 ++++++---- > .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 12 ++++++---- > .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 8 ++++--- > .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 8 ++++--- > .../drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 8 ++++--- > .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 12 ++++++---- > .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 6 +++-- > .../drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 12 ++++++---- > .../gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 12 ++++++---- > .../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 12 ++++++---- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 15 ++++++++++++ > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 6 +++-- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 27 ++++++++++++++++++++++ > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 4 ++++ > 15 files changed, 125 insertions(+), 41 deletions(-) If there is v3 for some reason, please split this into two patches: core/interrups and SoC catalog changes. -- With best wishes Dmitry