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Mon, 22 Jun 2026 04:01:42 -0700 (PDT) X-Received: by 2002:a05:6808:4f22:b0:48b:f341:1148 with SMTP id 5614622812f47-48bf34123afmr3761687b6e.3.1782126101919; Mon, 22 Jun 2026 04:01:41 -0700 (PDT) Received: from [192.168.120.170] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c0c60ac98c9sm336066766b.29.2026.06.22.04.01.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 22 Jun 2026 04:01:41 -0700 (PDT) Message-ID: Date: Mon, 22 Jun 2026 13:01:39 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/3] powercap: qcom: Add SPEL powercap driver To: Manaf Meethalavalappu Pallikunhi , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Bjorn Andersson , Konrad Dybcio , Daniel Lezcano Cc: Gaurav Kohli , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org References: <20260620-qcom_spel_driver_upstream-v2-0-a3ee6837c18f@oss.qualcomm.com> <20260620-qcom_spel_driver_upstream-v2-2-a3ee6837c18f@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260620-qcom_spel_driver_upstream-v2-2-a3ee6837c18f@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYwNjIyMDEwOCBTYWx0ZWRfX92rEScACvqdO PC4r0TeP/ZXnSb3yRfHRJWxo4MX9tLq/nU2pIrMODEPqggFMb3catPQXSpOigNKyox/IDLPz2Hm wNnXMm9KATCgK75b3/j1M0HM52KGrLA= X-Proofpoint-ORIG-GUID: MSXSaANYS0ozdZjIdgK0ntLp1Tc2zJgY X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjIyMDEwOCBTYWx0ZWRfX8pgEAG0d8KD7 iZvUKxcFMXsrFBgcPsgycBBEXlRC3Z+n19N+DknjFY0C1SftX1y6uUcp86R/U9k3w3P/kcwuTHn SZDUj4zg80asTtSlZVQ7zPopFcwqTuuWJy7Bp2uiDQOtwqu26n1nCzDP3zWEKEtUiZwbVzpRhRU L8P5Pd5knO7soRBN91YkHHXINZqp9Tcx7IlhMYYMkNU8oVsVoXGcIId3Fq6EY0RQtZ/lJMJ14Ta 2Cn0pHazQL3NV+apH9+uvxC0H2nb8nZtfmgSWCkJ9bXjXWhsCCdZR4HVNuvrxqj58oZDkX7Uqqv 8NC0N0lmwOmq/DYBhbdV5ERDqU1soKKPPx62W6eJ3kSy74msuHB8vnaP85UNdiLsYPdxCcIBRKK +y2ZqmwwMMTWV6PnXGAPuQHrSCixWeUDNYzTExTgHGd4T6Nq5xm0KXJiq2FGFTim+Kh/LrBnLuF YX6Wvpz0xUS+neuJ0tA== X-Proofpoint-GUID: MSXSaANYS0ozdZjIdgK0ntLp1Tc2zJgY X-Authority-Analysis: v=2.4 cv=cKbQdFeN c=1 sm=1 tr=0 ts=6a391617 cx=c_pps a=4ztaESFFfuz8Af0l9swBwA==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=02jEIrHkWd2Y-gyNavAA:9 a=QEXdDO2ut3YA:10 a=TPnrazJqx2CeVZ-ItzZ-:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-22_02,2026-06-18_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 adultscore=0 phishscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 impostorscore=0 suspectscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606220108 On 6/19/26 10:39 PM, Manaf Meethalavalappu Pallikunhi wrote: > The Qualcomm SoC Power and Electrical Limits (SPEL) provides hardware > based power monitoring and limiting capabilities for various power > domains including System, SoC, CPU clusters, GPU, and various other > subsystems. > > The driver integrates with the Linux powercap framework, exposing SPEL > capabilities through powercap sysfs interfaces. > > Signed-off-by: Manaf Meethalavalappu Pallikunhi > --- [...] > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include Please ensure all the includes are necessary > + > +/* SPEL register bitmasks */ > +#define ENERGY_STATUS_MASK GENMASK(31, 0) > + > +#define POWER_LIMIT_MASK GENMASK(14, 0) > +#define POWER_LIMIT_ENABLE BIT(31) > + > +#define TIME_WINDOW_MASK_L GENMASK(14, 0) > +#define TIME_WINDOW_MASK_H GENMASK(22, 16) Is BIT(15) not part of this? [...] > +/* Domain configuration */ > +static const struct spel_domain_info domain_info[SPEL_DOMAIN_MAX] = { > + [SPEL_DOMAIN_SYS] = { "sys", 0x40 }, > + [SPEL_DOMAIN_SOC] = { "soc", 0x00 }, > + [SPEL_DOMAIN_CL0] = { "cl0", 0x5c }, > + [SPEL_DOMAIN_CL1] = { "cl1", 0x60 }, > + [SPEL_DOMAIN_CL2] = { "cl2", 0x64 }, > + [SPEL_DOMAIN_IGPU] = { "igpu", 0x08 }, > + [SPEL_DOMAIN_DGPU] = { "dgpu", 0x44 }, > + [SPEL_DOMAIN_NSP] = { "nsp", 0x0c }, > + [SPEL_DOMAIN_MMCX] = { "mmcx", 0x10 }, > + [SPEL_DOMAIN_INFRA] = { "infra", 0x18 }, > + [SPEL_DOMAIN_DRAM] = { "dram", 0x1c }, > + [SPEL_DOMAIN_MDM] = { "mdm", 0x48 }, > + [SPEL_DOMAIN_WLAN] = { "wlan", 0x4c }, > + [SPEL_DOMAIN_USB1] = { "usb1", 0x50 }, > + [SPEL_DOMAIN_USB2] = { "usb2", 0x54 }, > + [SPEL_DOMAIN_USB3] = { "usb3", 0x58 }, > +}; I would expect that the names are going to stay common, but the offsets will be different. This array should probably be called glymur_domain_info[]. We may have another LUT just for names of indices (i.e. [SPEL_DOMAIN_xxx] = "xxx") > + > +/** > + * struct spel_constraint_info - Power limit constraint information > + * @limit_offset: Register offset for power limit value > + * @time_window_offset: Register offset for time window > + * @supported_mask: Bit mask in capability register > + * @domain_id: Domain this constraint applies to > + * @pl_id: Power limit ID (PL1, PL2, etc.) > + */ > +struct spel_constraint_info { > + u32 limit_offset; > + u32 time_window_offset; > + u32 supported_mask; > + enum spel_domain_type domain_id; > + int pl_id; > +}; > + > +/* Constraint configuration */ > +static const struct spel_constraint_info constraints[] = { > + /* SYS domain constraints */ > + { 0x10, 0x70, BIT(0), SPEL_DOMAIN_SYS, POWER_LIMIT1 }, > + { 0x14, 0x74, BIT(1), SPEL_DOMAIN_SYS, POWER_LIMIT2 }, > + { 0x18, 0x78, BIT(2), SPEL_DOMAIN_SYS, POWER_LIMIT3 }, > + { 0x1c, 0x7c, BIT(3), SPEL_DOMAIN_SYS, POWER_LIMIT4 }, > + /* SoC domain constraints */ > + { 0x00, 0x60, BIT(4), SPEL_DOMAIN_SOC, POWER_LIMIT1 }, > + { 0x04, 0x64, BIT(5), SPEL_DOMAIN_SOC, POWER_LIMIT2 }, > + { 0x08, 0x68, BIT(6), SPEL_DOMAIN_SOC, POWER_LIMIT3 }, > + { 0x0c, 0x6c, BIT(7), SPEL_DOMAIN_SOC, POWER_LIMIT4 }, > +}; Is this specific to Glymur, or SPEL-wide? [...] > +/** > + * struct spel_system - SPEL system odd tab after '-' [...] > + case PL_LIMIT: > + new_val = spel_unit_xlate(sd, POWER_UNIT, value, 1); > + if (new_val > FIELD_MAX(POWER_LIMIT_MASK)) > + return -EINVAL; > + reg_val = (reg_val & ~POWER_LIMIT_MASK) | FIELD_PREP(POWER_LIMIT_MASK, new_val); FIELD_MODIFY() > + > + /* > + * Enable/Disable PL based on the value: > + * - If value is 0, disable the PL (clear enable bit) > + * - If value is non-zero, enable the PL (set enable bit) > + */ > + if (new_val == 0) > + reg_val &= ~POWER_LIMIT_ENABLE; > + else > + reg_val |= POWER_LIMIT_ENABLE; Likewise > + > + writel(reg_val, reg_addr); > + return 0; > + > + case PL_TIME_WINDOW: > + /* > + * Encode time window: upper 7 bits to [22:16], lower 15 bits to [14:0] > + */ > + new_val = spel_unit_xlate(sd, TIME_UNIT, value, 1); > + if (new_val > TIME_WINDOW_MAX) > + return -EINVAL; > + /* Read-modify-write to preserve other bits */ > + reg_val = (reg_val & ~(TIME_WINDOW_MASK_H | TIME_WINDOW_MASK_L)) | > + FIELD_PREP(TIME_WINDOW_MASK_H, new_val >> 15) | > + FIELD_PREP(TIME_WINDOW_MASK_L, new_val); Also here [...] > +static void spel_detect_powerlimit(struct spel_domain *sd) > +{ > + struct spel_system *sp = sd->sp; > + u32 capabilities; > + int i, j; > + > + capabilities = readl(sp->config_base + LIMITS_CAPABILITY_OFFSET); > + > + /* > + * Detect power limits from hardware capabilities. > + * Start from index 1 (POWER_LIMIT2) since PL1 is always enabled in spel_init_domains(). > + */ > + for (i = 1; i < ARRAY_SIZE(pl_names); i++) { int i = POWER_LIMIT2 (yeah, nowadays you can finally declare the iterator inside the loop in the kernel) Konrad