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Wed, 17 Dec 2025 23:43:56 -0800 (PST) Message-ID: Date: Thu, 18 Dec 2025 09:43:54 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 2/6] dmaengine: sh: rz-dmac: Move all CHCTRL updates under spinlock To: Biju Das , "vkoul@kernel.org" , Fabrizio Castro , "geert+renesas@glider.be" , Prabhakar Mahadev Lad Cc: "dmaengine@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Claudiu Beznea , "stable@vger.kernel.org" References: <20251217135213.400280-1-claudiu.beznea.uj@bp.renesas.com> <20251217135213.400280-3-claudiu.beznea.uj@bp.renesas.com> Content-Language: en-US From: Claudiu Beznea In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi, Biju, On 12/17/25 18:16, Biju Das wrote: > Hi Claudiu, > >> -----Original Message----- >> From: Claudiu >> Sent: 17 December 2025 13:52 >> To: vkoul@kernel.org; Fabrizio Castro ; Biju Das >> ; geert+renesas@glider.be; Prabhakar Mahadev Lad > lad.rj@bp.renesas.com> >> Cc: Claudiu.Beznea ; dmaengine@vger.kernel.org; linux- >> kernel@vger.kernel.org; Claudiu Beznea ; stable@vger.kernel.org >> Subject: [PATCH v5 2/6] dmaengine: sh: rz-dmac: Move all CHCTRL updates under spinlock >> >> From: Claudiu Beznea >> >> Both rz_dmac_disable_hw() and rz_dmac_irq_handle_channel() update the CHCTRL registers. To avoid >> concurrency issues when updating these registers, take the virtual channel lock. All other CHCTRL >> updates were already protected by the same lock. >> >> Previously, rz_dmac_disable_hw() disabled and re-enabled local IRQs, before accessing CHCTRL registers >> but this does not ensure race-free access. > > Maybe I am missing some thing here about race-access: > > local_irq_save(flags); > rz_dmac_ch_writel(channel, CHCTRL_DEFAULT, CHCTRL, 1); > > After local_irq_save there won't be any IRQ. So how there > can be a race in IRQ handler. My point was to address races that may happen b/w different cores trying to set CHCTRL. E.g.: core0: take the IRQ and set CHCTRL core1: call rz_dmac_issue_pending() -> rz_dmac_xfer_desc() -> rz_dmac_enable_hw() -> set CHCTRL However, looking again though the HW manual, the CHCTRL returns zero when it is read, for each individual bit. Thus, there is no need for any kind of locking around this register. Also, read-modify-write approach when updating settings though it is not needed. I'll adjust it in the next version. Thank you, Claudiu