From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC4E3C46467 for ; Thu, 5 Jan 2023 01:56:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229836AbjAEBz7 convert rfc822-to-8bit (ORCPT ); Wed, 4 Jan 2023 20:55:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39954 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229508AbjAEBz4 (ORCPT ); Wed, 4 Jan 2023 20:55:56 -0500 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9D350DE86; Wed, 4 Jan 2023 17:55:54 -0800 (PST) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 4F55424E1AB; Thu, 5 Jan 2023 09:55:53 +0800 (CST) Received: from EXMBX067.cuchost.com (172.16.6.67) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 5 Jan 2023 09:55:53 +0800 Received: from EXMBX161.cuchost.com (172.16.6.71) by EXMBX067.cuchost.com (172.16.6.67) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 5 Jan 2023 09:55:52 +0800 Received: from EXMBX161.cuchost.com ([fe80::f152:b9a3:2243:db3c]) by EXMBX161.cuchost.com ([fe80::f152:b9a3:2243:db3c%15]) with mapi id 15.00.1497.044; Thu, 5 Jan 2023 09:55:52 +0800 From: Leyfoon Tan To: Conor Dooley , "palmer@dabbelt.com" CC: Conor Dooley , Sudeep Holla , Rob Herring , Krzysztof Kozlowski , Jonathan Corbet , "Alex Shi" , Yanteng Si , "Lorenzo Pieralisi" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-riscv@lists.infradead.org" , "linux-doc@vger.kernel.org" Subject: RE: [PATCH v1 2/2] dt-bindings: riscv: add a capacity-dmips-mhz cpu property Thread-Topic: [PATCH v1 2/2] dt-bindings: riscv: add a capacity-dmips-mhz cpu property Thread-Index: AQHZIGc9BMS8YNU6e0GmWB/Wrj6HBK6PEFog Date: Thu, 5 Jan 2023 01:55:52 +0000 Message-ID: References: <20230104180513.1379453-1-conor@kernel.org> <20230104180513.1379453-3-conor@kernel.org> In-Reply-To: <20230104180513.1379453-3-conor@kernel.org> Accept-Language: en-US, zh-CN Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [202.188.176.82] x-yovoleruleagent: yovoleflag Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > -----Original Message----- > > From: Conor Dooley > > Since commit 03f11f03dbfe ("RISC-V: Parse cpu topology during boot.") RISC- > V has used the generic arch topology code, which provides for disparate CPU > capacities. We never defined a binding to acquire this information from the > DT though, so document the one already used by the generic arch topology > code: "capacity-dmips-mhz". > > Signed-off-by: Conor Dooley > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml > b/Documentation/devicetree/bindings/riscv/cpus.yaml > index c6720764e765..2480c2460759 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -114,6 +114,12 @@ properties: > List of phandles to idle state nodes supported > by this hart (see ./idle-states.yaml). > > + capacity-dmips-mhz: > + description: > + u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in > + DMIPS/MHz, relative to highest capacity-dmips-mhz > + in the system. > + > required: > - riscv,isa > - interrupt-controller > -- > 2.39.0 Thanks Conor. Reviewed-by: Ley Foon Tan Regards Ley Foon