From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F926C433DF for ; Thu, 9 Jul 2020 23:01:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0505D20672 for ; Thu, 9 Jul 2020 23:01:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726961AbgGIXBV (ORCPT ); Thu, 9 Jul 2020 19:01:21 -0400 Received: from mga11.intel.com ([192.55.52.93]:60393 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726222AbgGIXBV (ORCPT ); Thu, 9 Jul 2020 19:01:21 -0400 IronPort-SDR: dhFpA58UcUriWsYFzhAoibE/fwRCqfRB935CYxGwL4ZFCKY08ugnS+k2Wwu99zvb2BF6ms04zf /blW/LjcggOg== X-IronPort-AV: E=McAfee;i="6000,8403,9677"; a="146196087" X-IronPort-AV: E=Sophos;i="5.75,332,1589266800"; d="scan'208";a="146196087" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jul 2020 16:01:10 -0700 IronPort-SDR: DG3QtNk9a5QLz1T9EUeee0oA9qnhYwzmQYBxQcSqbSxcw/cW6AGNEmPAP6A95Ag21WaBmUKiD0 Y+l6ter8sjvg== X-IronPort-AV: E=Sophos;i="5.75,332,1589266800"; d="scan'208";a="458083361" Received: from srinatha-mobl1.amr.corp.intel.com (HELO [10.255.5.187]) ([10.255.5.187]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jul 2020 16:01:09 -0700 Subject: Re: [tip: perf/core] x86/cpufeatures: Add Architectural LBRs feature bit To: linux-kernel@vger.kernel.org Cc: Kan Liang , "Peter Zijlstra (Intel)" , x86 References: <1593780569-62993-2-git-send-email-kan.liang@linux.intel.com> <159420191583.4006.10876391642907607745.tip-bot2@tip-bot2> From: Dave Hansen Autocrypt: addr=dave.hansen@intel.com; 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Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 MIME-Version: 1.0 In-Reply-To: <159420191583.4006.10876391642907607745.tip-bot2@tip-bot2> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 7/8/20 2:51 AM, tip-bot2 for Kan Liang wrote: > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > index 02dabc9..72ba4c5 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -366,6 +366,7 @@ > #define X86_FEATURE_MD_CLEAR (18*32+10) /* VERW clears CPU buffers */ > #define X86_FEATURE_TSX_FORCE_ABORT (18*32+13) /* "" TSX_FORCE_ABORT */ > #define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */ > +#define X86_FEATURE_ARCH_LBR (18*32+19) /* Intel ARCH LBR */ > #define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */ > #define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */ > #define X86_FEATURE_FLUSH_L1D (18*32+28) /* Flush L1D cache */ Are architectural LBRs useful *without* XSAVE? If not, should we add an entry in arch/x86/kernel/cpu/cpuid-deps.c::cpuid_deps[] for this? ... { X86_FEATURE_ARCH_LBR, X86_FEATURE_XSAVES }, ...