From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C73DEB64DC for ; Wed, 14 Jun 2023 19:35:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234427AbjFNTf2 (ORCPT ); Wed, 14 Jun 2023 15:35:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55926 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230523AbjFNTfU (ORCPT ); Wed, 14 Jun 2023 15:35:20 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 90F4FD2; Wed, 14 Jun 2023 12:35:19 -0700 (PDT) Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 35EJZBPI030174; Wed, 14 Jun 2023 19:35:12 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=message-id : date : mime-version : subject : to : cc : references : from : in-reply-to : content-type : content-transfer-encoding; s=qcppdkim1; bh=9smSbFVYl82f+y/0KvPf4pXAb2iOQ5rRfgVv9UilEJE=; b=CLH13HWekOApEclfAY8p0xRXDaBoT6ODvLz9tXy+jQav+iDsdPJOMBrtAEcaptsH9aVl fBx8+EWky9Hhvvv0TGIceFcLUOkpdthVWbLJKyeNaxVGubR+Er1atcUSKkJgopZpSADt ilaNvMnAdyWqxj9+oT2T2zugnKjv8z1CfAdggs+5MmxtewJdudKk1XKTEVXsJEKvX+OE jlZwHtI4aDAbMvdXiRymmSFcyuBgJQTYZEMwBPRhiHzminkyBNws8Y+ambx8cImLAVzc S9T4SO+PRhMCnf4itoRgXY9id2fsizSI8iKrRLs4wmzN75/6+7KPtJgpvETqhPaWzqby sA== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3r6t0buj3e-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 14 Jun 2023 19:35:11 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 35EJZA04026364 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 14 Jun 2023 19:35:10 GMT Received: from [10.134.70.142] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Wed, 14 Jun 2023 12:35:09 -0700 Message-ID: Date: Wed, 14 Jun 2023 12:35:09 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH 1/3] drm/msm/dpu: Add DPU_INTF_DATABUS_WIDEN feature flag for DPU >= 5.0 Content-Language: en-US To: Marijn Suijten , Dmitry Baryshkov CC: Jessica Zhang , Rob Clark , Sean Paul , David Airlie , Daniel Vetter , , , , References: <20230525-add-widebus-support-v1-0-c7069f2efca1@quicinc.com> <20230525-add-widebus-support-v1-1-c7069f2efca1@quicinc.com> From: Abhinav Kumar In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: vFnl2QgVphnnQvaMF-iMauUzAS0VmAdy X-Proofpoint-ORIG-GUID: vFnl2QgVphnnQvaMF-iMauUzAS0VmAdy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-14_14,2023-06-14_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 bulkscore=0 priorityscore=1501 clxscore=1015 mlxlogscore=999 spamscore=0 lowpriorityscore=0 suspectscore=0 adultscore=0 impostorscore=0 phishscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306140172 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 6/14/2023 5:23 AM, Marijn Suijten wrote: > On 2023-06-14 15:01:59, Dmitry Baryshkov wrote: >> On 14/06/2023 14:42, Marijn Suijten wrote: >>> On 2023-06-13 18:57:11, Jessica Zhang wrote: >>>> DPU 5.x+ supports a databus widen mode that allows more data to be sent >>>> per pclk. Enable this feature flag on all relevant chipsets. >>>> >>>> Signed-off-by: Jessica Zhang >>>> --- >>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 ++- >>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 ++ >>>> 2 files changed, 4 insertions(+), 1 deletion(-) >>>> >>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >>>> index 36ba3f58dcdf..0be7bf0bfc41 100644 >>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >>>> @@ -103,7 +103,8 @@ >>>> (BIT(DPU_INTF_INPUT_CTRL) | \ >>>> BIT(DPU_INTF_TE) | \ >>>> BIT(DPU_INTF_STATUS_SUPPORTED) | \ >>>> - BIT(DPU_DATA_HCTL_EN)) >>>> + BIT(DPU_DATA_HCTL_EN) | \ >>>> + BIT(DPU_INTF_DATABUS_WIDEN)) >>> >>> This doesn't work. DPU 5.0.0 is SM8150, which has DSI 6G 2.3. In the >>> last patch for DSI you state and enable widebus for DSI 6G 2.5+ only, >>> meaning DPU and DSI are now desynced, and the output is completely >>> corrupted. > > Tested this on SM8350 which actually has DSI 2.5, and it is also > corrupted with this series so something else on this series might be > broken. > >>> Is the bound in dsi_host wrong, or do DPU and DSI need to communicate >>> when widebus will be enabled, based on DPU && DSI supporting it? >> >> I'd prefer to follow the second approach, as we did for DP. DPU asks the >> actual video output driver if widebus is to be enabled. > I was afraid of this. This series was made on an assumption that the DPU version of widebus and DSI version of widebus would be compatible but looks like already SM8150 is an outlier. Yes, I think we have to go with second approach. DPU queries DSI if it supports widebus and enables it. Thanks for your responses. We will post a v2. > Doesn't it seem very strange that DPU 5.x+ comes with a widebus feature, > but the DSI does not until two revisions later? Or is this available on > every interface, but only for a different (probably DP) encoder block? > Yes its strange. > - Marijn