From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from canpmsgout03.his.huawei.com (canpmsgout03.his.huawei.com [113.46.200.218]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5DD6A14ABE for ; Wed, 29 Jul 2026 04:03:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.218 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785297829; cv=none; b=LQrG7ISfnekMEPUelEvcUTs30RslaHnFafbaW4d+KGg/GZJHTD3OsHqEq+Y+LcrPtner9BFICWKDetVv72jFATRcAH5w+G5wOHUnc0s+6p/fPdOyGI30zMSQgdD9kvEPM+H+TIVcvMGDgRLMGBovI5vXFBAIa6VQdhIHPuR4GQw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785297829; c=relaxed/simple; bh=6BQaG+nq/cpmm6NqV6JRpkJyG3RnlyTEnfxR1aEhcZA=; h=Message-ID:Date:MIME-Version:Subject:To:CC:References:From: In-Reply-To:Content-Type; b=ucC8GwvPUKjqM4z2LAn8VrWuxrFWyiEo/91yTxEIBzGA8S+iPqx3JaCrbUwUGEf6H/xoIeaZvOld2rg2MA0iMJVpw6g2DdN9scNCw2WwD5dnzX2oSTND78GVJQbCAapTE/JGH3qQGNHIxtwVmHAm3bieFLfRQgs932VG+b7ETeY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b=QQTQUSXE; arc=none smtp.client-ip=113.46.200.218 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b="QQTQUSXE" dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=CtxMSCKPf+Wkvxjg59JNH0r+l1IpWdwQef0QPwiYwRU=; b=QQTQUSXE5bcIbql9XtaH44Hmjk3s80+QgXa320Nob/iTVDkDG11zqneVzQwJGYOzuJAqUNBsP xdRk/blw8GIIHr09qT21JJez413QyXERYatIQ9b1d6UwKqOjTLZNfj+wlnSPhyzz1cG3vu59ZFn 7DteTHYyavVXxmKXj3VJ75o= Received: from mail.maildlp.com (unknown [172.19.162.144]) by canpmsgout03.his.huawei.com (SkyGuard) with ESMTPS id 4h8z3f3066zpSvQ; Wed, 29 Jul 2026 11:54:22 +0800 (CST) Received: from dggpemf500011.china.huawei.com (unknown [7.185.36.131]) by mail.maildlp.com (Postfix) with ESMTPS id 57D2D40538; Wed, 29 Jul 2026 12:03:39 +0800 (CST) Received: from [10.67.109.254] (10.67.109.254) by dggpemf500011.china.huawei.com (7.185.36.131) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 29 Jul 2026 12:03:38 +0800 Message-ID: Date: Wed, 29 Jul 2026 12:03:37 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH 04/13] arm64: percpu: Factor out percpu offset asm To: Mark Rutland , CC: , , , , , , , , , References: <20260728123859.2911495-1-mark.rutland@arm.com> <20260728123859.2911495-5-mark.rutland@arm.com> From: Jinjie Ruan In-Reply-To: <20260728123859.2911495-5-mark.rutland@arm.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-ClientProxiedBy: kwepems200002.china.huawei.com (7.221.188.68) To dggpemf500011.china.huawei.com (7.185.36.131) 在 2026/7/28 20:38, Mark Rutland 写道: > Depending on whether the kernel runs at EL1 or EL2, the percpu offset is > stored in either TPIDR_EL1 or TPIDR_EL2, and __kern_my_cpu_offset() uses > an ALTERNATIVE() sequence to read the relevant TPIDR_ELx. > > In subsequent patches we'll need to read the percpu offset in other > assembly sequences. Factor the ALTERNATIVE sequence out of > __kern_my_cpu_offset() into a new __KERN_ASM_CPU_OFFSET() macro so that > we can share the code sequence. Reviewed-by: Jinjie Ruan > > There should be no functional change as a result of this patch. > > Signed-off-by: Mark Rutland > Cc: Ada Couprie Diaz > Cc: Ard Biesheuvel > Cc: Catalin Marinas > Cc: Jinjie Ruan > Cc: Marc Zyngier > Cc: Peter Zijlstra > Cc: Vladimir Murzin > Cc: Will Deacon > Cc: Yang Shi > --- > arch/arm64/include/asm/percpu.h | 15 ++++++++++----- > 1 file changed, 10 insertions(+), 5 deletions(-) > > diff --git a/arch/arm64/include/asm/percpu.h b/arch/arm64/include/asm/percpu.h > index b57b2bb009677..98823c97d534c 100644 > --- a/arch/arm64/include/asm/percpu.h > +++ b/arch/arm64/include/asm/percpu.h > @@ -29,6 +29,11 @@ static inline unsigned long __hyp_my_cpu_offset(void) > return read_sysreg(tpidr_el2); > } > > +#define __KERN_ASM_CPU_OFFSET(dst) \ > + ALTERNATIVE("mrs " dst ", tpidr_el1", \ > + "mrs " dst ", tpidr_el2", \ > + ARM64_HAS_VIRT_HOST_EXTN) > + > static inline unsigned long __kern_my_cpu_offset(void) > { > unsigned long off; > @@ -37,11 +42,11 @@ static inline unsigned long __kern_my_cpu_offset(void) > * We want to allow caching the value, so avoid using volatile and > * instead use a fake stack read to hazard against barrier(). > */ > - asm(ALTERNATIVE("mrs %0, tpidr_el1", > - "mrs %0, tpidr_el2", > - ARM64_HAS_VIRT_HOST_EXTN) > - : "=r" (off) : > - "Q" (*(const unsigned long *)current_stack_pointer)); > + asm( > + __KERN_ASM_CPU_OFFSET("%0") > + : "=r" (off) > + : "Q" (*(const unsigned long *)current_stack_pointer) > + ); > > return off; > }