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Thu, 29 Oct 2026 11:14:09 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 X-ThreadId: AkBENj9svcUo Date: Thu, 29 Oct 2026 16:13:49 +0100 From: "Arnd Bergmann" To: "Julian Vetter" , "David S . Miller" , "Andreas Larsson" Cc: sparclinux@vger.kernel.org, linux-kernel@vger.kernel.org Message-Id: In-Reply-To: <20261029145309.132218-1-julian@outer-limits.org> References: <20261029145309.132218-1-julian@outer-limits.org> Subject: Re: [PATCH] sparc: Remove IO memcpy and memset from sparc code Content-Type: text/plain Content-Transfer-Encoding: 7bit On Thu, Oct 29, 2026, at 15:53, Julian Vetter wrote: > Remove the IO memcpy and memset from sparc specific code and fall back > to the implementations from lib/iomem_copy.c. They use word accesses if > the buffers are aligned and only fall back to byte accesses for > potentially unaligned parts of a buffer, while the sparc versions always > use byte-wise readb()/writeb() accesses. Other architectures, such as > arm64, csky, loongarch and parisc, have already been converted to the > generic implementation. > > This does not drop any memory barriers. The sparc versions don't use > mb(), and the rmb()/wmb() implied by readb()/writeb() on sparc32 and > sparc64 are only compiler barriers. Hi Julian, I suspect the sparc64 patch is wrong because the generic code relies on __raw_readq()/__raw_readl() to produce native-endian data, while the sparc64 version looks like they work on little-endian data the same way as readq()/readl(). Do you know if the PCI host bridge on sparc64 does an implicit byte swap for memory space? If it does, the __raw_ accessors have to flip swap the data another time for this to work. Arnd