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Thu, 22 Oct 2026 02:34:32 -0700 (PDT) Received: from [192.168.226.26] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c468a55c001sm84619866b.31.2026.10.22.02.34.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 22 Oct 2026 02:34:31 -0700 (PDT) Message-ID: Date: Thu, 22 Oct 2026 11:34:29 +0200 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] arm64: dts: qcom: monaco-evk: Describe the PCIe M.2 Key E connector To: Loic Poulain Cc: Manivannan Sadhasivam , Wei Deng , andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-bluetooth@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, quic_chezhou@quicinc.com, cheng.jiang@oss.qualcomm.com, shuai.zhang@oss.qualcomm.com, jinwang.li@oss.qualcomm.com, xiuzhuo.shang@oss.qualcomm.com, mengshi.wu@oss.qualcomm.com References: <0303224f-4c2c-46ec-9866-5ea1fd0fb4a3@oss.qualcomm.com> <20260825092715.5794-1-wei.deng@oss.qualcomm.com> <83b67ab2-ab68-427a-94aa-881454f457ba@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; 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Konrad >>>> suggested moving the port/endpoint anchor nodes to the SoC DTSI >>>> (monaco.dtsi) for clean DTS layering, so that board files only need to >>>> fill in remote-endpoint for boards that actually have an M.2 connector. >>>> >>> >>> This means, the dummy port/endpoint node will always be present even when the >>> M.2 connector is not used. I don't see a compelling reason to do so. >> >> I don't really see a compelling reason to defer re-defining them to each >> device DT either.. > > Adding an empty port/endpoint at the SoC level is problematic for > uart, port is not always expected, this depends if the uart is exposed > through a connector or to an onboard device. So we may end with an > unconnected endpoint but still have a bluetooth subnode, which can be > a bit confusing... Also why adding a port/endpoint only for a specific > uart in the dts, and not for the others? This is a board/SoC level > choice to use a specific uart for M2 or not. >From my perspective it's removing boilerplate. Currently all USB and PCIe hosts already define their ports and endpoints in the SoC DTSI and if they're unconnected, then simply nothing happens. Both 'ports' and 'endpoints' are an abstract property that signify 'X can be related to Y' and I don't see how that's a problem here given UART is very much expected to be connected "somewhere" (with the "somewhere" perhaps being external/a pin header) Konrad