From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 96B53287519; Thu, 8 May 2025 18:51:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746730321; cv=none; b=X7PmaK1Vw3ccOFJ3lc0bFVS80QhJ9VrbnwHfFreBjE6XHr5GlWKVkVQ7/dTc9xc5qHv116+kCr4ku8SVNcO6X3EgP3wDcnRdQdlrNsSQPXLRxW16aJdATWJvpwOf4Sl12oICg/CaX599UcoAxwbM6fmEBFEvnngO9i6/v4kRJ2I= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746730321; c=relaxed/simple; bh=CReeJ5GZcLHpi5oAFgB9nNLBduTT9q1ZWDivz9sFLpg=; h=Message-ID:Date:MIME-Version:Subject:To:CC:References:From: In-Reply-To:Content-Type; b=XPsZe3rFC2auKwitfRobp1A2Cjz4lvG98qkmZj5/pfYJYck8eT3xn9QQgvijtXtE0StD1GAjMn1i9n0fCR0lbAA00difmm8bOdtJN1tARXk+x0p7nKb8bH5qa00bDKkE1S6Xyeexpqo1Y3I9NLSUZ13BWvGutvqrSOa0P0RIvAU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=PSkj8yB9; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="PSkj8yB9" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 548D1gl0008543; Thu, 8 May 2025 18:51:47 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= nAhTFtF9g1tx91/xJc7I9vKl5NCFCa2Z5q1ubiwoD20=; b=PSkj8yB9bLqz9qnR f7DrS/wwDqZuB9UiS+dPypNJjA9XuT3Cx51pxU+KABY6R948UdFRPfxmJL7oIMqs R+Aj+fNWUkc07ZJW9nSljXjCs80xtknLiF9RNxn3rxF7YgJUrAP+2cgP3K7u40iG BPOMh38mmZ1GrB1T/MUFLg18M9KWlYPFo/v5roYYTWi6PjqGO1pjO1FBh+V0GM2E VufwkbnPoxUYf3ay2dGZZJsys99wlBBy5/R21M8D2Wwe+3lg+LzTFtsTKC9YWDpx ePef6wrnsF6mJuDctht92mG+LOhM60I8QHbVsBonaA2OPQwXsIMhTiXmRyq7T1y2 l3qo7Q== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 46gnp5aa5n-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 08 May 2025 18:51:46 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 548IpaYe020383 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 8 May 2025 18:51:36 GMT Received: from [10.134.71.99] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 8 May 2025 11:51:36 -0700 Message-ID: Date: Thu, 8 May 2025 11:51:35 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v9 12/14] drm/msm/dpu: support SSPP assignment for quad-pipe case To: Jun Nie , Rob Clark , "Abhinav Kumar" , Sean Paul , "Marijn Suijten" , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Dmitry Baryshkov CC: , , , References: <20250506-quad-pipe-upstream-v9-0-f7b273a8cc80@linaro.org> <20250506-quad-pipe-upstream-v9-12-f7b273a8cc80@linaro.org> Content-Language: en-US From: Jessica Zhang In-Reply-To: <20250506-quad-pipe-upstream-v9-12-f7b273a8cc80@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=Lu2Symdc c=1 sm=1 tr=0 ts=681cfd42 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=sWKEhP36mHoA:10 a=KKAkSRfTAAAA:8 a=-8mmxbYOZCIPUL7Q3dcA:9 a=QEXdDO2ut3YA:10 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: MAOm37N2AeoJ7Rf56QukW8ll2AYrT7fd X-Proofpoint-ORIG-GUID: MAOm37N2AeoJ7Rf56QukW8ll2AYrT7fd X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTA4MDE2OCBTYWx0ZWRfX7G/MeYojYmmW RoLQjaHj08nE5yy4phHW1OvPRnoenqpI3CvVGA+nugKGRogcux+WWHVHp3qpul4CYFDy2zBropb LRP1h0dWemB12cxpLEmRvzpO4k7VRocMPhITx3BcZqyKmkROnfrWtz1YQM2f2iPKMZO0i/KBWnv bfmVXseo4hOCH5Ox5KE+H34gPlrU5PqI6RmIUZbBWsMoM1+IqkPbQj4+JaErWOG2pwfJiqUtyIe 1XnjA5zU64TZp394cPnyz94QWUjIgdRSFfA7FI7oN6NllNncq7b3hchpQ/IYhqMImoI/bDJUCtb XV/T1gnMlygGxbywHZtDISZwa270sbgl9itxdKc+2Y3weBAISySeCstbz3QmlTWaHqDid9xYFbT WZuPKGutgLwrrwbTmISipabrShPe55UtdPcK+3YsyimcuvPl9ZEqUdwJ7HTcvLZ2fBPzGsVK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-08_06,2025-05-08_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 bulkscore=0 mlxlogscore=999 priorityscore=1501 suspectscore=0 clxscore=1015 adultscore=0 malwarescore=0 spamscore=0 impostorscore=0 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505080168 On 5/6/2025 8:47 AM, Jun Nie wrote: > Currently, SSPPs are assigned to a maximum of two pipes. However, > quad-pipe usage scenarios require four pipes and involve configuring > two stages. In quad-pipe case, the first two pipes share a set of > mixer configurations and enable multi-rect mode when certain > conditions are met. The same applies to the subsequent two pipes. > > Assign SSPPs to the pipes in each stage using a unified method and > to loop the stages accordingly. > > Signed-off-by: Jun Nie > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 68 +++++++++++++++++++------------ > 1 file changed, 42 insertions(+), 26 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > index ea7e3fdf52f726737941ad33218a843dca17280b..de3f52d743e1d1f11ae8721a316b9872d4139069 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > @@ -1112,11 +1112,10 @@ static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc, > struct dpu_rm_sspp_requirements reqs; > struct dpu_plane_state *pstate; > struct dpu_sw_pipe *pipe; > - struct dpu_sw_pipe *r_pipe; > struct dpu_sw_pipe_cfg *pipe_cfg; > - struct dpu_sw_pipe_cfg *r_pipe_cfg; > + struct dpu_plane *pdpu = to_dpu_plane(plane); > const struct msm_format *fmt; > - int i; > + int i, num_lm, stage_id, num_stages; > > if (plane_state->crtc) > crtc_state = drm_atomic_get_new_crtc_state(state, > @@ -1124,11 +1123,6 @@ static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc, > > pstate = to_dpu_plane_state(plane_state); > > - pipe = &pstate->pipe[0]; > - r_pipe = &pstate->pipe[1]; > - pipe_cfg = &pstate->pipe_cfg[0]; > - r_pipe_cfg = &pstate->pipe_cfg[1]; > - > for (i = 0; i < PIPES_PER_PLANE; i++) > pstate->pipe[i].sspp = NULL; > > @@ -1142,24 +1136,46 @@ static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc, > > reqs.rot90 = drm_rotation_90_or_270(plane_state->rotation); > > - pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &reqs); > - if (!pipe->sspp) > - return -ENODEV; > - > - if (!dpu_plane_try_multirect_parallel(pipe, pipe_cfg, r_pipe, r_pipe_cfg, > - pipe->sspp, > - msm_framebuffer_format(plane_state->fb), > - dpu_kms->catalog->caps->max_linewidth)) { > - /* multirect is not possible, use two SSPP blocks */ > - r_pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &reqs); > - if (!r_pipe->sspp) > - return -ENODEV; > - > - pipe->multirect_index = DPU_SSPP_RECT_SOLO; > - pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; > - > - r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; > - r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; > + num_lm = dpu_crtc_get_num_lm(crtc_state); Hi Jun, I think there might be some patch ordering issue here since `dpu_crtc_get_num_lm()` is only declared/defined in the next patch. This will break compilation upon partial application of the series. Also, can you rebase this on top of the latest msm-next? The changes here will conflict with commit 3ed12a36 ("drm/msm/dpu: allow sharing SSPP between planes"). Thanks, Jessica Zhang > + num_stages = (num_lm + 1) / 2; > + for (stage_id = 0; stage_id < num_stages; stage_id++) { > + for (i = stage_id * PIPES_PER_STAGE; i < (stage_id + 1) * PIPES_PER_STAGE; i++) { > + struct dpu_sw_pipe *r_pipe; > + struct dpu_sw_pipe_cfg *r_pipe_cfg; > + > + pipe = &pstate->pipe[i]; > + pipe_cfg = &pstate->pipe_cfg[i]; > + > + if (drm_rect_width(&pipe_cfg->src_rect) == 0) > + break; > + > + pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &reqs); > + if (!pipe->sspp) > + return -ENODEV; > + > + r_pipe = &pstate->pipe[i + 1]; > + r_pipe_cfg = &pstate->pipe_cfg[i + 1]; > + > + /* > + * If current pipe is the first pipe in pipe pair, check > + * multi-rect opportunity for the 2nd pipe in the pair. > + * SSPP multi-rect mode cross mixer pairs is not supported. > + */ > + if ((i % PIPES_PER_STAGE == 0) && > + drm_rect_width(&r_pipe_cfg->src_rect) != 0 && > + dpu_plane_try_multirect_parallel(pipe, pipe_cfg, r_pipe, r_pipe_cfg, > + pipe->sspp, > + msm_framebuffer_format(plane_state->fb), > + dpu_kms->catalog->caps->max_linewidth)) { > + i++; > + } else { > + /* multirect is not possible, use two SSPP blocks */ > + pipe->multirect_index = DPU_SSPP_RECT_SOLO; > + pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; > + DPU_DEBUG_PLANE(pdpu, "allocating sspp_%d for pipe %d.\n", > + pipe->sspp->idx - SSPP_NONE, i); > + } > + } > } > > return dpu_plane_atomic_check_sspp(plane, state, crtc_state); >