From: Lizhi Hou <lizhi.hou@amd.com>
To: Geert Uytterhoeven <geert@linux-m68k.org>, <nishad.saraf@amd.com>
Cc: <vkoul@kernel.org>, <dmaengine@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, Nishad Saraf <nishads@amd.com>,
<sonal.santan@amd.com>, <max.zhen@amd.com>
Subject: Re: [PATCH V12 1/1] dmaengine: amd: qdma: Add AMD QDMA driver
Date: Tue, 3 Sep 2024 09:50:46 -0700 [thread overview]
Message-ID: <e2a37bb6-3353-1c2f-3841-d63748756df1@amd.com> (raw)
In-Reply-To: <CAMuHMdXVoTx8K+Vppt07s06OE6R=4BxoBbgtp1WWkCi8DwqgSA@mail.gmail.com>
On 9/3/24 02:20, Geert Uytterhoeven wrote:
> Hi Lizhi, Nishad,
>
> On Thu, Apr 18, 2024 at 7:51 PM Lizhi Hou <lizhi.hou@amd.com> wrote:
>> From: Nishad Saraf <nishads@amd.com>
>>
>> Adds driver to enable PCIe board which uses AMD QDMA (the Queue-based
>> Direct Memory Access) subsystem. For example, Xilinx Alveo V70 AI
>> Accelerator devices.
>> https://www.xilinx.com/applications/data-center/v70.html
>>
>> The QDMA subsystem is used in conjunction with the PCI Express IP block
>> to provide high performance data transfer between host memory and the
>> card's DMA subsystem.
>>
>> +-------+ +-------+ +-----------+
>> PCIe | | | | | |
>> Tx/Rx | | | | AXI | |
>> <=======> | PCIE | <===> | QDMA | <====>| User Logic|
>> | | | | | |
>> +-------+ +-------+ +-----------+
>>
>> The primary mechanism to transfer data using the QDMA is for the QDMA
>> engine to operate on instructions (descriptors) provided by the host
>> operating system. Using the descriptors, the QDMA can move data in both
>> the Host to Card (H2C) direction, or the Card to Host (C2H) direction.
>> The QDMA provides a per-queue basis option whether DMA traffic goes
>> to an AXI4 memory map (MM) interface or to an AXI4-Stream interface.
>>
>> The hardware detail is provided by
>> https://docs.xilinx.com/r/en-US/pg302-qdma
>>
>> Implements dmaengine APIs to support MM DMA transfers.
>> - probe the available DMA channels
>> - use dma_slave_map for channel lookup
>> - use virtual channel to manage dmaengine tx descriptors
>> - implement device_prep_slave_sg callback to handle host scatter gather
>> list
>>
>> Signed-off-by: Nishad Saraf <nishads@amd.com>
>> Signed-off-by: Lizhi Hou <lizhi.hou@amd.com>
> Thanks for your patch, which is now commit 73d5fc92a11cacb7
> ("dmaengine: amd: qdma: Add AMD QDMA driver") in dmaengine/next.
>
>> --- /dev/null
>> +++ b/drivers/dma/amd/Kconfig
>> @@ -0,0 +1,14 @@
>> +# SPDX-License-Identifier: GPL-2.0-only
>> +
>> +config AMD_QDMA
>> + tristate "AMD Queue-based DMA"
>> + depends on HAS_IOMEM
> Any other subsystem or platform dependencies, to prevent asking the
> user about this driver when configuring a kernel for a system which
> cannot possibly have this hardware?
> E.g. depends on PCI, or can this be used with other transports than PCIe?
No, this driver does not have other dependencies. It can be used with
other transports.
It is similar with dmaengine/xilinx/xdma
Thanks,
Lizhi
>
>> --- /dev/null
>> +++ b/drivers/dma/amd/qdma/qdma-comm-regs.c
>> +static struct platform_driver amd_qdma_driver = {
>> + .driver = {
>> + .name = "amd-qdma",
> Which code is responsible for creating "amd-qdma" platform devices?
>
>> + },
>> + .probe = amd_qdma_probe,
>> + .remove_new = amd_qdma_remove,
>> +};
>> +
>> +module_platform_driver(amd_qdma_driver);
> Gr{oetje,eeting}s,
>
> Geert
>
next prev parent reply other threads:[~2024-09-03 16:50 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-18 17:50 [PATCH V12 0/1] " Lizhi Hou
2024-04-18 17:50 ` [PATCH V12 1/1] dmaengine: amd: qdma: Add " Lizhi Hou
2024-09-03 9:20 ` Geert Uytterhoeven
2024-09-03 16:50 ` Lizhi Hou [this message]
2024-09-27 9:01 ` Geert Uytterhoeven
2024-09-27 18:18 ` Lizhi Hou
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