From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E11AC54EAA for ; Mon, 30 Jan 2023 09:42:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235728AbjA3JmY (ORCPT ); Mon, 30 Jan 2023 04:42:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48638 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235757AbjA3JmO (ORCPT ); Mon, 30 Jan 2023 04:42:14 -0500 Received: from mail-sh.amlogic.com (mail-sh.amlogic.com [58.32.228.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 97A482111; Mon, 30 Jan 2023 01:41:17 -0800 (PST) Received: from [10.18.29.47] (10.18.29.47) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.13; Mon, 30 Jan 2023 17:41:14 +0800 Message-ID: Date: Mon, 30 Jan 2023 17:41:14 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH V6 3/3] clk: meson: s4: add support for Amlogic S4 SoC peripheral clock controller Content-Language: en-US To: Jerome Brunet , , , , , , Rob Herring , Neil Armstrong , Kevin Hilman , Michael Turquette , Stephen Boyd , Krzysztof Kozlowski , Martin Blumenstingl CC: "kelvin . zhang" , "qi . duan" References: <20230116074214.2326-1-yu.tu@amlogic.com> <20230116074214.2326-4-yu.tu@amlogic.com> <1ja62eybrv.fsf@starbuckisacylon.baylibre.com> <1jwn5hwn0w.fsf@starbuckisacylon.baylibre.com> <1jy1pko0fc.fsf@starbuckisacylon.baylibre.com> From: Yu Tu In-Reply-To: <1jy1pko0fc.fsf@starbuckisacylon.baylibre.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.18.29.47] X-ClientProxiedBy: mail-sh.amlogic.com (10.18.11.5) To mail-sh.amlogic.com (10.18.11.5) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2023/1/30 17:06, Jerome Brunet wrote: > [ EXTERNAL EMAIL ] > > > On Sat 28 Jan 2023 at 18:17, Yu Tu wrote: > >> On 2023/1/20 17:47, Jerome Brunet wrote: >>> [ EXTERNAL EMAIL ] >>> On Fri 20 Jan 2023 at 11:33, Yu Tu wrote: >>> >>>> Hi >>>> On 2023/1/19 19:37, Jerome Brunet wrote: >>>>> [ EXTERNAL EMAIL ] >>>>> On Mon 16 Jan 2023 at 15:42, Yu Tu wrote: >>>>> >>>>>> Add the peripherals clock controller driver in the s4 SoC family. >>>>>> >>>>>> Signed-off-by: Yu Tu >>>>> [...] >>>>> >>>>>> + >>>>>> +/* Video Clocks */ >>>>>> +static struct clk_regmap s4_vid_pll_div = { >>>>>> + .data = &(struct meson_vid_pll_div_data){ >>>>>> + .val = { >>>>>> + .reg_off = CLKCTRL_VID_PLL_CLK_DIV, >>>>>> + .shift = 0, >>>>>> + .width = 15, >>>>>> + }, >>>>>> + .sel = { >>>>>> + .reg_off = CLKCTRL_VID_PLL_CLK_DIV, >>>>>> + .shift = 16, >>>>>> + .width = 2, >>>>>> + }, >>>>>> + }, >>>>>> + .hw.init = &(struct clk_init_data) { >>>>>> + .name = "vid_pll_div", >>>>>> + /* >>>>>> + * The frequency division from the hdmi_pll clock to the vid_pll_div >>>>>> + * clock is the default value of this register. When designing the >>>>>> + * video module of the chip, a default value that can meet the >>>>>> + * requirements of the video module will be solidified according >>>>>> + * to the usage requirements of the chip, so as to facilitate chip >>>>>> + * simulation. So this is ro_ops. >>>>>> + * It is important to note that this clock is not used on this >>>>>> + * chip and is described only for the integrity of the clock tree. >>>>>> + */ >>>>> If it is reset value and will be applicable to all the design, regarless >>>>> of the use-case, then yes RO ops is OK >>>>> >>>>> >From what I understand here, the value will depend on the use-case requirements. >>>>> This is a typical case where the DT prop "assigned-rate" should be used, not RO ops. >>>> >>>> Check the previous chip history, the actual scene is not used at all, >>>> basically is used in simulation. So the previous SOC was "ro_ops" without >>>> any problems. This S4 SOC is not actually useful either. >>>> >>>> So when you were upstream, you had no problem making "ro_ops". I wonder if >>>> I could delete this useless clock, so you don't have to worry about it. >>> I don't know what to make of this. What is the point of adding a useless >>> clock ? >> >> As explained earlier this "vid_pll_div" is actually used in chip >> emulation. So next I'd like to know what you suggest to do with the clock? >> > > If it does not exist in the actual SoC, please remove it > If I remove it, the "vid_pll_sel" clock will be missing a parent (vid_pll_div). I will use the table method and give the above reasons. Do you accept this method?