From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965550AbdEYLe5 (ORCPT ); Thu, 25 May 2017 07:34:57 -0400 Received: from foss.arm.com ([217.140.101.70]:49068 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965516AbdEYLeu (ORCPT ); Thu, 25 May 2017 07:34:50 -0400 Cc: Sudeep Holla , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/4] arm64: dts: mt7622: add basic nodes to the mt7622.dtsi file To: sean.wang@mediatek.com, robh+dt@kernel.org, matthias.bgg@gmail.com, mark.rutland@arm.com, devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org References: From: Sudeep Holla Organization: ARM Message-ID: Date: Thu, 25 May 2017 12:34:28 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.1.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 25/05/17 10:28, sean.wang@mediatek.com wrote: > From: Sean Wang > > add basic nodes into the mt7622.dtsi for the system > bring-up which includes ARM CPU, GIC, timer, MediaTek > UART, SYSIRQ and one reserved memory region for ATF. > > Signed-off-by: Sean Wang > --- > arch/arm64/boot/dts/mediatek/mt7622.dtsi | 103 +++++++++++++++++++++++++++++++ > 1 file changed, 103 insertions(+) > create mode 100644 arch/arm64/boot/dts/mediatek/mt7622.dtsi > > diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi > new file mode 100644 > index 0000000..f610d30 > --- /dev/null > +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi > @@ -0,0 +1,103 @@ > +/* > + * Copyright (c) 2017 MediaTek Inc. > + * Author: Ming Huang > + * Sean Wang > + * > + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) > + */ > + > +#include > +#include > + > +/ { > + compatible = "mediatek,mt7622"; > + interrupt-parent = <&sysirq>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53", "arm,armv8"; > + reg = <0x0 0x0>; > + enable-method = "psci"; > + next-level-cache = <&l2>; Just note that cache geometry detection from architected registers are removed from v4.12 and hence needs to be specified in DT if you expect it to show up in sysfs. -- Regards, Sudeep