From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9BB78C433EF for ; Thu, 26 May 2022 08:22:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346648AbiEZIWn (ORCPT ); Thu, 26 May 2022 04:22:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36060 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344875AbiEZIWi (ORCPT ); Thu, 26 May 2022 04:22:38 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 80931C1EF1; Thu, 26 May 2022 01:22:36 -0700 (PDT) X-UUID: cca026dc720b4357a7fd5e82a9abd24f-20220526 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:6d0ff8da-95d9-42a5-b1b0-56d4e6acc1d3,OB:10,L OB:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,AC TION:release,TS:45 X-CID-INFO: VERSION:1.1.5,REQID:6d0ff8da-95d9-42a5-b1b0-56d4e6acc1d3,OB:10,LOB :0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:45 X-CID-META: VersionHash:2a19b09,CLOUDID:8f9653b8-3c45-407b-8f66-25095432a27a,C OID:22bc0917443f,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:0,BEC:nil X-UUID: cca026dc720b4357a7fd5e82a9abd24f-20220526 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1728256351; Thu, 26 May 2022 16:22:33 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Thu, 26 May 2022 16:22:32 +0800 Received: from mhfsdcap04 (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Thu, 26 May 2022 16:22:29 +0800 Message-ID: Subject: Re: [PATCH v2 3/7] iommu: mtk_iommu: Lookup phandle to retrieve syscon to pericfg From: Yong Wu To: AngeloGioacchino Del Regno CC: , , , , , , , , , , Date: Thu, 26 May 2022 16:22:28 +0800 In-Reply-To: <20220518100503.37279-4-angelogioacchino.delregno@collabora.com> References: <20220518100503.37279-1-angelogioacchino.delregno@collabora.com> <20220518100503.37279-4-angelogioacchino.delregno@collabora.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 2022-05-18 at 12:04 +0200, AngeloGioacchino Del Regno wrote: > On some SoCs (of which only MT8195 is supported at the time of > writing), > the "R" and "W" (I/O) enable bits for the IOMMUs are in the > pericfg_ao > register space and not in the IOMMU space: as it happened already > with > infracfg, it is expected that this list will grow. > > Instead of specifying pericfg compatibles on a per-SoC basis, > following > what was done with infracfg, let's lookup the syscon by phandle > instead. > Also following the previous infracfg change, add a warning for > outdated > devicetrees, in hope that the user will take action. > > Signed-off-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > --- > drivers/iommu/mtk_iommu.c | 26 ++++++++++++++++---------- > 1 file changed, 16 insertions(+), 10 deletions(-) > > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > index d16b95e71ded..090cf6e15f85 100644 > --- a/drivers/iommu/mtk_iommu.c > +++ b/drivers/iommu/mtk_iommu.c > @@ -138,6 +138,8 @@ > /* PM and clock always on. e.g. infra iommu */ > #define PM_CLK_AO BIT(15) > #define IFA_IOMMU_PCIE_SUPPORT BIT(16) > +/* IOMMU I/O (r/w) is enabled using PERICFG_IOMMU_1 register */ > +#define HAS_PERI_IOMMU1_REG BIT(17) > > #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \ > ((((pdata)->flags) & (mask)) == (_x)) > @@ -187,7 +189,6 @@ struct mtk_iommu_plat_data { > u32 flags; > u32 inv_sel_reg; > > - char *pericfg_comp_str; > struct list_head *hw_list; > unsigned int iova_region_nr; > const struct mtk_iommu_iova_region *iova_region; > @@ -1214,14 +1215,19 @@ static int mtk_iommu_probe(struct > platform_device *pdev) > goto out_runtime_disable; > } > } else if (MTK_IOMMU_IS_TYPE(data->plat_data, > MTK_IOMMU_TYPE_INFRA) && > - data->plat_data->pericfg_comp_str) { > - infracfg = syscon_regmap_lookup_by_compatible(data- > >plat_data->pericfg_comp_str); > - if (IS_ERR(infracfg)) { > - ret = PTR_ERR(infracfg); > - goto out_runtime_disable; > - } > + MTK_IOMMU_HAS_FLAG(data->plat_data, > HAS_PERI_IOMMU1_REG)) { > + data->pericfg = syscon_regmap_lookup_by_phandle(dev- > >of_node, "mediatek,pericfg"); I'm not keen to add this property. Currently only mt8195 use this setting. In the lastest SoC, we move this setting to ATF. thus I think we could keep the current way, no need add a new DT property only for mt8195. > + if (IS_ERR(data->pericfg)) { > + dev_info(dev, "Cannot find phandle to > mediatek,pericfg:" > + " Please update your > devicetree.\n"); > > - data->pericfg = infracfg; > + p = "mediatek,mt8195-pericfg_ao"; > + data->pericfg = > syscon_regmap_lookup_by_compatible(p); > + if (IS_ERR(data->pericfg)) { > + ret = PTR_ERR(data->pericfg); > + goto out_runtime_disable; > + } > + } > } > > platform_set_drvdata(pdev, data); > @@ -1480,8 +1486,8 @@ static const struct mtk_iommu_plat_data > mt8192_data = { > static const struct mtk_iommu_plat_data mt8195_data_infra = { > .m4u_plat = M4U_MT8195, > .flags = WR_THROT_EN | DCM_DISABLE | STD_AXI_MODE | > PM_CLK_AO | > - MTK_IOMMU_TYPE_INFRA | > IFA_IOMMU_PCIE_SUPPORT, > - .pericfg_comp_str = "mediatek,mt8195-pericfg_ao", > + HAS_PERI_IOMMU1_REG | MTK_IOMMU_TYPE_INFRA > | > + IFA_IOMMU_PCIE_SUPPORT, > .inv_sel_reg = REG_MMU_INV_SEL_GEN2, > .banks_num = 5, > .banks_enable = {true, false, false, false, true},