From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751600AbdBHUJO (ORCPT ); Wed, 8 Feb 2017 15:09:14 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:41064 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751002AbdBHUJE (ORCPT ); Wed, 8 Feb 2017 15:09:04 -0500 DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org C312C6087F Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=cov@codeaurora.org Subject: Re: [PATCH v6] arm64: Work around Falkor erratum 1003 To: Catalin Marinas References: <20170208003516.9519-1-cov@codeaurora.org> <20170208163441.GC32756@e104818-lin.cambridge.arm.com> Cc: Jonathan Corbet , Marc Zyngier , Will Deacon , linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Mark Rutland , linux-kernel@vger.kernel.org, shankerd@codeaurora.org, timur@codeaurora.org, Jon Masters , Neil Leeder , Mark Langsdorf , Mark Salter From: Christopher Covington Message-ID: Date: Wed, 8 Feb 2017 15:09:00 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.2 MIME-Version: 1.0 In-Reply-To: <20170208163441.GC32756@e104818-lin.cambridge.arm.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 02/08/2017 11:34 AM, Catalin Marinas wrote: > On Tue, Feb 07, 2017 at 07:35:16PM -0500, Christopher Covington wrote: >> --- a/arch/arm64/Kconfig >> +++ b/arch/arm64/Kconfig >> @@ -480,6 +480,18 @@ config CAVIUM_ERRATUM_27456 >> >> If unsure, say Y. >> >> +config QCOM_FALKOR_ERRATUM_1003 >> + bool "Falkor E1003: Incorrect translation due to ASID change" >> + default y >> + select ARM64_PAN if ARM64_SW_TTBR0_PAN >> + help >> + On Falkor v1, an incorrect ASID may be cached in the TLB when ASID >> + and BADDR are changed together in TTBRx_EL1. The workaround for this >> + issue is to use a reserved ASID in cpu_do_switch_mm() before >> + switching to the new ASID. >> + >> + If unsure, say Y. > > It would be good to have a comment here on why PAN is selected. > >> --- a/arch/arm64/mm/context.c >> +++ b/arch/arm64/mm/context.c >> @@ -79,6 +79,13 @@ void verify_cpu_asid_bits(void) >> } >> } >> >> +static void set_reserved_asid_bits(void) >> +{ >> + if (IS_ENABLED(CONFIG_QCOM_FALKOR_ERRATUM_1003) && >> + cpus_have_cap(ARM64_WORKAROUND_QCOM_FALKOR_E1003)) >> + __set_bit(FALKOR_RESERVED_ASID, asid_map); >> +} > > You should use cpus_have_const_cap() as it would be optimised using jump > labels. Thanks Catalin. Done in v7. Cov -- Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.