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This > memory is typically used by MCU R5 firmware for low latency accesses. > > Signed-off-by: Hari Nagalla > Signed-off-by: Judith Mendez > Signed-off-by: Sai Sree Kartheek Adivi > --- > .../arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi > index 2394a4fb5a94c..278404cadcd98 100644 > --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi > @@ -6,6 +6,18 @@ > */ > > &cbass_mcu { > + mcu_ram: sram@79100000 { > + compatible = "mmio-sram"; > + reg = <0x00 0x79100000 0x00 0x80000>; > + ranges = <0x00 0x00 0x79100000 0x80000>; > + #address-cells = <1>; > + #size-cells = <1>; > + commit message says, 2 banks of 256Kb, Here you have only 1 block. Please add description, why you are adding 1 block only > + mcu1-sram@0 { > + reg = <0x0 0x80000>; > + }; what is use of this ?, If you really need this then, please make it block of 256Kb (something like below) mcu-sram-0 { reg = <0x0 0x40000>; }; mcu-sram-1 { reg = <0x40000 0x40000>; }; > + }; > + > mcu_pmx0: pinctrl@4084000 { > compatible = "pinctrl-single"; > reg = <0x00 0x04084000 0x00 0x88>;