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a=rsa-sha256; c=relaxed/relaxed; d=ew.tq-group.com; s=dkim; t=1758715174; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=GVeEbXZHLLVdgtkq3Rt5skmTBi/qzB86iEFJYe7MbOY=; b=MiszbaIwL75n4NinMTq+BtlT448qY1P4vjFdNNNxGvnFo5VbY/XtEhFJx57K1X2drvQ8Wy eFHuNGbe+zA4jYso57yNiZDcPKjj30UANNnydpV8lMLt57Qz+2EdIANvQtyZDigrVlQRP2 ThjtrAKGiMQhwQsXr6tTKoFhNeEKosH0CIqKc413ZDZQT3PRPlHH5KPEvWtCg7lyokJQMr Aey54GL7SRvgoJW7b44SH158DUntQm3nCjEN3ztKX8uwwlMUPP9tRmr9yFey34nuOXa2wm hRE4qUWIuBCM5kLf0QgnbQukWDG7pgJpaA8scFRKpdpXB/ChxnDRiWOQdBDXMQ== Message-ID: Subject: Re: [PATCH v6 1/2] arm64: entry: Skip single stepping into interrupt handlers From: Matthias Schiffer To: Sumit Garg Cc: mark.rutland@arm.com, daniel.thompson@linaro.org, dianders@chromium.org, liwei391@huawei.com, mhiramat@kernel.org, maz@kernel.org, ardb@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, will@kernel.org, catalin.marinas@arm.com, linux@ew.tq-group.com Date: Wed, 24 Sep 2025 13:59:32 +0200 In-Reply-To: <20230202073148.657746-2-sumit.garg@linaro.org> References: <20230202073148.657746-1-sumit.garg@linaro.org> <20230202073148.657746-2-sumit.garg@linaro.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.52.3-0ubuntu1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 On Thu, 2023-02-02 at 13:01 +0530, Sumit Garg wrote: > Currently on systems where the timer interrupt (or any other > fast-at-human-scale periodic interrupt) is active then it is impossible > to step any code with interrupts unlocked because we will always end up > stepping into the timer interrupt instead of stepping the user code. >=20 > The common user's goal while single stepping is that when they step then > the system will stop at PC+4 or PC+I for a branch that gets taken > relative to the instruction they are stepping. So, fix broken single step > implementation via skipping single stepping into interrupt handlers. >=20 > The methodology is when we receive an interrupt from EL1, check if we > are single stepping (pstate.SS). If yes then we save MDSCR_EL1.SS and > clear the register bit if it was set. Then unmask only D and leave I set. > On return from the interrupt, set D and restore MDSCR_EL1.SS. Along with > this skip reschedule if we were stepping. >=20 > Suggested-by: Will Deacon > Signed-off-by: Sumit Garg > Tested-by: Douglas Anderson > Acked-by: Daniel Thompson > Tested-by: Daniel Thompson Hi Sumit, I was wondering what the status of this patch is. [1] sounds like there wer= e remaining concerns, but I'm not sure about the details. The current state is very unsatisfactory, as I need to apply this patch eve= ry time I want to use KGDB on arm64. It is not only required for single-steppi= ng, but it also fixes 'continue' endlessly hitting the same breakpoint (until t= he breakpoint is deleted or disabled). Best, Matthias [1] https://lkml.org/lkml/2023/2/22/49 > --- > arch/arm64/kernel/entry-common.c | 22 ++++++++++++++++++++-- > 1 file changed, 20 insertions(+), 2 deletions(-) >=20 > diff --git a/arch/arm64/kernel/entry-common.c b/arch/arm64/kernel/entry-c= ommon.c > index cce1167199e3..568481f66977 100644 > --- a/arch/arm64/kernel/entry-common.c > +++ b/arch/arm64/kernel/entry-common.c > @@ -231,11 +231,15 @@ DEFINE_STATIC_KEY_TRUE(sk_dynamic_irqentry_exit_con= d_resched); > #define need_irq_preemption() (IS_ENABLED(CONFIG_PREEMPTION)) > #endif > =20 > -static void __sched arm64_preempt_schedule_irq(void) > +static void __sched arm64_preempt_schedule_irq(struct pt_regs *regs) > { > if (!need_irq_preemption()) > return; > =20 > + /* Don't reschedule in case we are single stepping */ > + if (regs->pstate & DBG_SPSR_SS) > + return; > + > /* > * Note: thread_info::preempt_count includes both thread_info::count > * and thread_info::need_resched, and is not equivalent to > @@ -471,19 +475,33 @@ static __always_inline void __el1_irq(struct pt_reg= s *regs, > do_interrupt_handler(regs, handler); > irq_exit_rcu(); > =20 > - arm64_preempt_schedule_irq(); > + arm64_preempt_schedule_irq(regs); > =20 > exit_to_kernel_mode(regs); > } > + > static void noinstr el1_interrupt(struct pt_regs *regs, > void (*handler)(struct pt_regs *)) > { > + unsigned long mdscr; > + > + /* Disable single stepping within interrupt handler */ > + if (regs->pstate & DBG_SPSR_SS) { > + mdscr =3D read_sysreg(mdscr_el1); > + write_sysreg(mdscr & ~DBG_MDSCR_SS, mdscr_el1); > + } > + > write_sysreg(DAIF_PROCCTX_NOIRQ, daif); > =20 > if (IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) && !interrupts_enabled(regs)) > __el1_pnmi(regs, handler); > else > __el1_irq(regs, handler); > + > + if (regs->pstate & DBG_SPSR_SS) { > + write_sysreg(DAIF_PROCCTX_NOIRQ | PSR_D_BIT, daif); > + write_sysreg(mdscr, mdscr_el1); > + } > } > =20 > asmlinkage void noinstr el1h_64_irq_handler(struct pt_regs *regs) --=20 TQ-Systems GmbH | M=C3=BChlstra=C3=9Fe 2, Gut Delling | 82229 Seefeld, Germ= any Amtsgericht M=C3=BCnchen, HRB 105018 Gesch=C3=A4ftsf=C3=BChrer: Detlef Schneider, R=C3=BCdiger Stahl, Stefan Sch= neider https://www.tq-group.com/