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Thu, 10 Sep 2026 16:17:31 -0700 From: Nicolin Chen To: , , , "Jonathan Cameron" CC: , , , , , , , Jean-Philippe Brucker , "Eric Auger" , , , , , , , , , Subject: [PATCH v4 09/15] iommu/arm-smmu-v3: Disable PRI when no IRQ handler is registered Date: Thu, 10 Sep 2026 16:17:01 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023CE:EE_|LV2PR12MB919616:EE_ X-MS-Office365-Filtering-Correlation-Id: 8ce3c047-fc76-40e6-937d-08df0f91bca9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|36860700016|1800799024|82310400026|23010399003|6133799003|11063799006|10067099003|56012099006|5023799004|22082099003|18002099003; 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These paths warn but leave ARM_SMMU_FEAT_PRI set. This function itself would then go on to enable IRQ_CTRL_PRIQ_IRQEN, even though no handler will drain the queue. A later patch also enables PRI on such endpoints. The caller already enabled CR0_PRIQEN before this function even runs. Clear ARM_SMMU_FEAT_PRI in all three failure paths, so that subsequent code treats PRI as unavailable. And disable CR0_PRIQEN after the setup function returns. A kdump kernel doesn't service page requests: strip FEAT_PRI when detecting features, so downstream PRI setup is skipped. Reviewed-by: Jonathan Cameron Assisted-by: Claude:claude-opus-4-8 Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index bd7615ce69581..43a6029cef430 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -4936,9 +4936,11 @@ static void arm_smmu_setup_unique_irqs(struct arm_smmu_device *smmu) dev_warn(smmu->dev, "failed to enable priq irq\n"); smmu->priq.q.irq = 0; + smmu->features &= ~ARM_SMMU_FEAT_PRI; } } else { dev_warn(smmu->dev, "no priq irq - PRI will be broken\n"); + smmu->features &= ~ARM_SMMU_FEAT_PRI; } } else { /* An unrequested IRQ (e.g. set by DT) must not be disabled */ @@ -4973,6 +4975,7 @@ static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu) if (ret < 0) { dev_warn(smmu->dev, "failed to enable combined irq\n"); smmu->combined_irq = 0; + smmu->features &= ~ARM_SMMU_FEAT_PRI; } } else arm_smmu_setup_unique_irqs(smmu); @@ -5153,6 +5156,10 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu) return ret; } + /* arm_smmu_setup_irqs() might have unset the ARM_SMMU_FEAT_PRI */ + if (!(smmu->features & ARM_SMMU_FEAT_PRI)) + enables &= ~CR0_PRIQEN; + if (is_kdump_kernel()) enables &= ~(CR0_EVTQEN | CR0_PRIQEN); @@ -5294,7 +5301,7 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu) } /* Boolean feature flags */ - if (IS_ENABLED(CONFIG_PCI_PRI) && reg & IDR0_PRI) + if (IS_ENABLED(CONFIG_PCI_PRI) && reg & IDR0_PRI && !is_kdump_kernel()) smmu->features |= ARM_SMMU_FEAT_PRI; if (IS_ENABLED(CONFIG_PCI_ATS) && reg & IDR0_ATS) -- 2.43.0