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c=relaxed/relaxed; s=zm2022; d=zohomail.com; v=1; bh=MejGJQjR0eeHynwaf2K0BI7CBc1IkI/gaC528fBJyx8=; h=Content-Description:Content-ID:Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Owner:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Resent-Sender:Resent-Cc:Resent-Date:Resent-To:Reply-To:Resent-Message-ID:Resent-From:Sender:Subject:To:Date:From:Message-Id:Reply-To:Subject:To:Cc; Received: by smtp.zohomail.com with SMTPS id 1793387493279176.3797193726208; Fri, 30 Oct 2026 12:11:33 -0700 (PDT) Message-ID: Date: Sat, 31 Oct 2026 03:11:29 +0800 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] cxl/port: Unmask AER internal errors for VH endpoints To: Richard Cheng , dave@stgolabs.net, jic23@kernel.org, dave.jiang@intel.com, alison.schofield@intel.com, vishal.l.verma@intel.com Cc: iweiny@kernel.org, linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org, kaihengf@nvidia.com, kobak@nvidia.com, newtonl@nvidia.com, kristinc@nvidia.com References: <20261030095951.46080-1-icheng@nvidia.com> From: Li Ming In-Reply-To: <20261030095951.46080-1-icheng@nvidia.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Feedback-ID: zu08011227d4cd3fe03e4dfbad211110320000564959910c5844141bd21f41fccaea78dcb22fb0611ecd4654:ZohoMail X-Zoho-CM-AccountID: abd763e7b9fa23acf4f42a44f9876d2d993e05abdb9290f9ccb1008c977bf7f0 X-ZohoMailClient: External On 10/30/2026 5:59 PM, Richard Cheng wrote: > CXL protocol errors are reported through PCIe AER internal errors. > Unmasking the endpoint's CXL RAS register alone leaves the AER internal > errors masked, thus the notification can't reach the Root Port. > > Unmask AER internal errors during native endpoint RAS setup for VH > devices. Allow cxl_port to use pci_aer_unmask_internal_errors() through > its module-restricted export. > > Verified with QEMU mem-data-ecc injection: the Root Port AER interrupt > fires, the CXL correctable-error trace is emitted, and the endpoint's > CorrIntErr counter increments. I found the similiar implementation[1] in CXL RAS support for VH patchset[2], seems like it is under review. [1]: https://lore.kernel.org/linux-cxl/20260902133933.2992457-9-terry.bowman@amd.com/ [2]: https://lore.kernel.org/linux-cxl/20260902133933.2992457-1-terry.bowman@amd.com/ Ming > > Signed-off-by: Richard Cheng > --- > drivers/cxl/port.c | 7 +++++++ > drivers/pci/pcie/aer.c | 3 ++- > 2 files changed, 9 insertions(+), 1 deletion(-) > > diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c > index c48216e5078f..c94a310061b0 100644 > --- a/drivers/cxl/port.c > +++ b/drivers/cxl/port.c > @@ -121,6 +121,13 @@ static int cxl_ras_unmask(struct cxl_port *port) > orig_val, val); > } > > + /* > + * RCH errors are reported by the RCEC. VH endpoints report CXL > + * protocol errors as PCIe AER internal errors. > + */ > + if (!is_cxl_restricted(pdev)) > + pci_aer_unmask_internal_errors(pdev); > + > return 0; > } > > diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c > index db4f607f889c..94eca22422b7 100644 > --- a/drivers/pci/pcie/aer.c > +++ b/drivers/pci/pcie/aer.c > @@ -1287,7 +1287,8 @@ void pci_aer_unmask_internal_errors(struct pci_dev *dev) > * Internal errors are too device-specific to enable generally, however for CXL > * their behavior is standardized for conveying CXL protocol errors. > */ > -EXPORT_SYMBOL_FOR_MODULES(pci_aer_unmask_internal_errors, "cxl_core"); > +EXPORT_SYMBOL_FOR_MODULES(pci_aer_unmask_internal_errors, > + "cxl_core,cxl_port"); > > #ifdef CONFIG_CXL_RAS > bool is_aer_internal_error(struct aer_err_info *info) > > base-commit: f0c48323b0402349530abc60ea908b5f5f40c395