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Thu, 02 Jul 2026 06:43:36 -0700 (PDT) X-Received: by 2002:a17:90a:d44b:b0:37c:7090:821b with SMTP id 98e67ed59e1d1-380aa0f436amr5638703a91.10.1782999816037; Thu, 02 Jul 2026 06:43:36 -0700 (PDT) Received: from [192.168.1.7] ([122.177.243.236]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-380e1636a03sm1154162a91.1.2026.07.02.06.43.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 02 Jul 2026 06:43:35 -0700 (PDT) Message-ID: Date: Thu, 2 Jul 2026 19:13:29 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] phy: qcom-qusb2: don't unrelated bits if autoresume is not used To: Konrad Dybcio , Dmitry Baryshkov , Wesley Cheng Cc: Vinod Koul , Neil Armstrong , Kathiravan T , Baruch Siach , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org References: <20260702-fix-qusb2-v1-0-b5cf55621524@oss.qualcomm.com> <20260702-fix-qusb2-v1-1-b5cf55621524@oss.qualcomm.com> <64f7efcc-1cd6-40f5-80c0-ab5f882854a3@oss.qualcomm.com> <3goo36jai5g2v24ijlf7g4gehq5zdlk7uwizya7dimqtm5pmrs@norf4xbqdlw5> <3c533783-e2a5-48f3-8275-4cef5651938b@oss.qualcomm.com> Content-Language: en-US From: Krishna Kurapati In-Reply-To: <3c533783-e2a5-48f3-8275-4cef5651938b@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: WyLmfhIbBg8_U2pPCUAeqSF4Q-cS8DYi X-Authority-Analysis: v=2.4 cv=a4kAM0SF c=1 sm=1 tr=0 ts=6a466b09 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=OtbC+xJwP8rERjI3u+ECAg==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=VwQbUJbxAAAA:8 a=COk6AnOGAAAA:8 a=OgPk0aSyYpcDEwaxJaMA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzAyMDE0MyBTYWx0ZWRfX+lakFMPCIKGm Bzd4KRJB45sVknhDgTJ/i2ACg1ZjY8f+lc8e1kC7FK4y0DWaQYF+Aezw73lcJNYZ4V4hDpDs+nG ivneyxKQTS231IoywpjcJMI1FDk83gYzV8nhes4lU1szOIRe/oIXTBn+6yy7RxiLaN/UsUaqnbo rbfHB4eayHK5I9n/FQrkAHEpMFncFH671DvzTMC84QG6ZdL1652qP55xYU6t5eb/McBMVTkKwOh da6u+IZqJGRmpIDXlk5tSLaai7Wt5qMMm9YAvoTwTuSThvz1FVEIiFloTScWSgUxwp1aj5tXQld po4eG5ILXiKPCxRuVuPiusxMzlhsp/KT+ZQGnco0XCgdB++nwwRSi5rm8I6ddgC7Egt05rFJg2t BaHJhAKrTaxAnSmgqDUkQN//cWUa9AslPWYixHr6e7avX9DTv0AnWGi8s4HY8B359lgc6TyWsQX zcJlxxZOfjbfAWCLmew== X-Proofpoint-Spam-Info: AW1haW4tMjYwNzAyMDE0MyBTYWx0ZWRfX0Whv54XoIdYq +EJTxYnzng7cUZ4UDltOZLl4wtLPAfXprom9eBIWoJKISYj3hV/mmbhKpMIOPKmKgToKjqBzfj6 MOObCeJeaLdenVL1yPdEj94deDWV0PE= X-Proofpoint-GUID: WyLmfhIbBg8_U2pPCUAeqSF4Q-cS8DYi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-07-02_01,2026-06-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 impostorscore=0 malwarescore=0 adultscore=0 suspectscore=0 priorityscore=1501 bulkscore=0 spamscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607020143 On 7/2/2026 5:54 PM, Konrad Dybcio wrote: > On 7/2/26 2:21 PM, Dmitry Baryshkov wrote: >> On Thu, Jul 02, 2026 at 02:00:06PM +0200, Konrad Dybcio wrote: >>> On 7/2/26 1:40 PM, Dmitry Baryshkov wrote: >>>> The IPQ6018 and QCS615 platforms don't need to toggle the autoresume >>>> bit. >>> >>> why? >> >> Here I have no idea, the HPG is unspecific, exact details are to be >> defined somewhere else. The platforms, when they were added, just stated >> that autoresume is to be skipped. Maybe original developers (in cc) can >> answer this question. Anyway, if autoresume is to be toggled, it should >> be coming as a separate fixup. I can reorder the patches though, so that >> at least register layout is correct. > > +Krishna, Wesley? > I checked downstream driver code and I see this: 1. If the phy is qusb2 v2, then we are setting and clearing BIT(0) of TEST1 register. 2. If the phy is qusb2, then we are setting and clearing BIT(3) of TEST_CTRL register. For both IPQ6018 and QCS615, I checked and its BIT(3) of TEST_CTRL register to be set. For msm8998 it is BIT(0) of TEST1 register. Also for qcs615, in downstream code, I see that auto-resume is being set. Its a mistake from my end when I added [1]. [1]: https://lore.kernel.org/all/20241014084432.3310114-5-quic_kriskura@quicinc.com/ Regards, Krishna,