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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id t17-20020a508d51000000b004acc44ad062sm2177063edt.61.2023.02.13.06.40.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 13 Feb 2023 06:40:58 -0800 (PST) Message-ID: Date: Mon, 13 Feb 2023 16:40:56 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.1 Subject: Re: [PATCH 05/10] drm/msm/dpu: Allow variable SSPP/INTF_BLK size Content-Language: en-GB To: Marijn Suijten Cc: Konrad Dybcio , linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org, Rob Clark , Abhinav Kumar , Sean Paul , David Airlie , Daniel Vetter , Robert Foss , AngeloGioacchino Del Regno , dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20230211122656.1479141-1-konrad.dybcio@linaro.org> <20230211122656.1479141-6-konrad.dybcio@linaro.org> <20230213111220.ietr4aro6xu4emtu@SoMainline.org> <20230213143148.qvyagudd3qm5jgwd@SoMainline.org> From: Dmitry Baryshkov In-Reply-To: <20230213143148.qvyagudd3qm5jgwd@SoMainline.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 13/02/2023 16:31, Marijn Suijten wrote: > On 2023-02-13 13:38:33, Dmitry Baryshkov wrote: >> On 13/02/2023 13:12, Marijn Suijten wrote: >>> On 2023-02-11 13:26:51, Konrad Dybcio wrote: >>>> These blocks are of variable length on different SoCs. Set the >>>> correct values where I was able to retrieve it from downstream >>>> DTs and leave the old defaults (0x1c8 for sspp and 0x280 for >>>> intf) otherwise. >>>> >>>> Signed-off-by: Konrad Dybcio >>>> --- >>>> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 242 +++++++++--------- >>>> 1 file changed, 121 insertions(+), 121 deletions(-) >>>> >>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >>>> index 802050118345..d9ef1e133c1e 100644 >>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >>> [..] >>>> @@ -1848,10 +1848,10 @@ static struct dpu_dsc_cfg sm8150_dsc[] = { >>>> /************************************************************* >>>> * INTF sub blocks config >>>> *************************************************************/ >>>> -#define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit) \ >>>> +#define INTF_BLK(_name, _id, _base, _len, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit) \ >>> >>> Dmitry and I discussed in #freedreno to instead add the INTF_BLK_DSI_TE >>> macro that accounts for the INTF TE registers using this higher register >>> area, as well as an extended signature to configure extra interrupts. >> >> Yes, that's still the plan. It's slightly painful that we are touching >> this are simultaneously. > > Should we (Konrad) then drop this patch as there's no need to add these > (mostly RAZ/WI) registers to the dump until my INTF TE series starts > using them? That'll make rebasing easier on everyone too. RAZ/WI is for not present registers (read-as-zero/write-ignore). I think that the growing register space is getting populated with registers (which we have been ignoring up to now). > > - Marijn > >>> (Besides, I think the len is currently only used for snapshot dumping >>> and no validation for out-of-blk reads/writes) >> >> Yes. Because in most of the cases non-existing registers seem to be RAZ/WI. >> >>> >>>> {\ >>>> .name = _name, .id = _id, \ >>>> - .base = _base, .len = 0x280, \ >>>> + .base = _base, .len = _len, \ >>>> .features = _features, \ >>>> .type = _type, \ >>>> .controller_id = _ctrl_id, \ >>> [..] >>> >>> - Marijn >> >> -- >> With best wishes >> Dmitry >> -- With best wishes Dmitry