Re: [PATCH v2 1/2] EDAC/amd64: Mask UMC chip select to the four implemented selects

["Badole, Vishal" <vishal.badole@amd.com>]

On 9/29/2026 10:25 PM, Yazen Ghannam wrote:
> On Mon, Sep 28, 2026 at 11:39:34PM +0530, Vishal Badole wrote:
>> umc_get_err_info() masks the Chip Select from MCA_SYND with 0x7, a
>> leftover from Zen 1 where the architecture reserved space for up to
>> eight chip selects. Only four have ever been implemented, and newer
>> products document this as MCA_SYND_UMC[1:0] = Chip Select.
>>
>> Since only four csrows are allocated, a syndrome with bit 2 set decodes
>> to an out-of-range csrow and trips:
>>
>>    EDAC MC0: INTERNAL ERROR: csrow value is out of range (5 >= 4)
>>
>> Mask with 0x3 to match the four implemented chip selects.
>>
>> Fixes: 713ad54675fd ("EDAC, amd64: Define and register UMC error decode function")
>> Cc: <stable@vger.kernel.org>
>> Suggested-by: Yazen Ghannam <yazen.ghannam@amd.com>
>> Signed-off-by: Vishal Badole <Vishal.Badole@amd.com>
>> Reviewed-by: Yazen Ghannam <yazen.ghannam@amd.com>
>> ---
>>   drivers/edac/amd64_edac.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
>> index 475235c402e8..ec4cc306b726 100644
>> --- a/drivers/edac/amd64_edac.c
>> +++ b/drivers/edac/amd64_edac.c
>> @@ -2802,7 +2802,7 @@ static inline void decode_bus_error(int node_id, struct mce *m)
>>   static void umc_get_err_info(struct mce *m, struct err_info *err)
>>   {
>>   	err->channel = (m->ipid & GENMASK(31, 0)) >> 20;
>> -	err->csrow = m->synd & 0x7;
>> +	err->csrow = m->synd & 0x3;
>>   }
>>   
>>   static void decode_umc_error(int node_id, struct mce *m)
>> -- 
> 
> I just noticed that the code comment above this function needs an update
> too.
Sure, I will correct it in the next patch revision.

> 
> Thanks,
> Yazen