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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: BuPU3YFex5zUdyaakRDfrg34LHM6HLKFh7mognSeV9iAhdDBp1rfsLK7TVwvrNrHWjHi9wcQz18EeVdcB8EG6Cni4kt2MyM7/zZdlszSLnGDQ2ukPvPZYjfVQpwwVZX/0ciKM9HAHuHreddJrkyH9dj/oWt6OsYlUC3SL4yD6SME8361j8LxIDG8OYxjDH4qgkcOIlppRfbvukNiRRQA7qLQsGiL669qCo3HbdLZFr6nrI80RgDGlpiVPAZV8KxG2ZxNRZDVuGNanCG+GsMLLPR+hP3oMOAgYMG+pgIZNAjb10B/B7t9Vi9sZLmHjuWqu1erCWZxwiqUnDcJi7it2a7HwsFmiarL7NMRgVNks8gvDkZlxRmvWQNv/QnQoh1QgUe7xeyClf7J8g+xns8waia1zk0e6I+1TFf+ujcxUmvW1kwJ/XcS2w096t84wSG1 X-OriginatorOrg: topic.nl X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2026 06:48:00.0840 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 085bd268-568b-4998-0564-08df34bf685e X-MS-Exchange-CrossTenant-Id: 449607a5-3517-482d-8d16-41dd868cbda3 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=449607a5-3517-482d-8d16-41dd868cbda3;Ip=[20.93.157.195];Helo=[westeu11-emailsignatures-cloud.codetwo.com] X-MS-Exchange-CrossTenant-AuthSource: WA1PEPF00009B39.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MA9PR04MB121114 On 10/28/26 03:19, Stephan Costa Barros wrote: > Hi Mike, > > On Mon, Oct 26, 2026 at 07:27:22AM +0100, Mike Looijmans wrote: >> On 25-10-2026 01:13, Stephan Costa Barros wrote: >>> - The datasheet powers up the supplies first, then the clock, then >>> waits t_POR =3D 2^18 clock cycles (128 ms at 2.048 MHz) before the >>> reset. The driver enabled an external clock and the vref supply >>> before AVDD, reset right away, and did not wait for the 150 ms >>> start-up of the internal reference. Follow the datasheet. Probe tak= es >>> about 280 ms longer. >> The driver followed the correct procedure: Keep reset asserted until the >> power is enabled. >> >> We've seen the chips misbehave when the power supplies ramp up >> erratically. Keeping them in reset until the power supplies are stable >> solves that issue, if a reset signal is available. The driver is based >> on real experience with these chips. > Thanks, that experience is what I lack here. > > The patch keeps that: RESET is still requested asserted before anything > is enabled, and released only after AVDD, VREF and the clock are on. > What changes is that AVDD now comes before the clock and VREF, and that > the driver waits t_POR before releasing RESET. "reset right away" meant > releasing it without that wait; I'll reword it. Ah, okay. > Is AVDD before the clock fine with you? Section 11.1 asks to keep all > digital inputs, CLK included, low until the supplies are stable. That sounds solid, better than it was. >> There is no need to wait for the internal reference startup. The >> internal reference only affects the ADC performance, it isn't required >> for digital communication. By the time userspace gets to use the driver, >> those 150 ms will have passed already. > Agreed, I'll drop that wait. > >> We actually have 8 (or more) of these chips on a single board. If it >> takes 8x 280 ms extra to boot such a board, it will fail to meet medical >> specs (reboot in 5 seconds). > Understood. Without the reference wait it is t_POR alone, 128 ms per > chip at 2.048 MHz, still about 1 s for 8 chips probed one after another. Which is still unreasonably long. We modelled this into the power supply. The 8 chips all share their power supplies, so the first to switch on will= =20 need the delay, but the others don't. So if you put a delay on the power=20 supply, only whatever device triggers it first will have to wait. All devic= es=20 that use that power supply will wait in parallel. And if the supply is on a= t=20 boot, there'll be no delay. >> The ADS1298 datasheet says "18" clock cycles, not "2^18". Quite a >> difference. We would definitely have noticed if the reset timeout was >> that far off. > I read 2^18 in the current revision, SBAS459K (August 2015), Table 38: > "t_POR, Wait after power up until reset, MIN 2^18 t_CLK", with the note > "When using an external clock, t_POR timing does not start until CLK is > valid". Its revision history lists "Changed power-up reset wait time in > Table 38", so older revisions may differ. The 18 t_CLK in Figure 105 is > the wait after the reset pulse, which the driver already does. The > ADS1299 datasheet (SBAS499C, Table 30) gives 2^18 t_CLK as well. Oh, you're quite right, I stand corrected. Don't recall it, it's been a whi= le=20 since I worked on that project. > That said, I have not seen the missing wait cause a failure on hardware. > On my board the supplies are up long before the driver probes, so t_POR > has passed by then, and that may be the case on yours too. Does the > driver switch the supplies on your boards, or are they on from boot? The AVDD is separate and shared, the DVDD is just always on (also powers th= e=20 CPU and a bunch of IO banks). But what I said before applies, the delay should be in the power supply. Th= en=20 all devices sharing that supply can wait in parallel. > > In v3 the supply order, the t_POR wait and the clock rate become > separate patches, as Jonathan asked, so each can be judged on its own. > > Regards, > Stephan Mike.