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AJvYcCV7jw8rQvgjuWL09G/NWKQIGbwO03d1e5n5WOvsFoCmCVEBn0hmvoHN6cLEFageIdVPt968PJdf3s1of+nngDIEiaqg5tc5A/67pIQB X-Gm-Message-State: AOJu0YxdNku6LX4jDnBooCtqlVJKIdDkynP6CNqfWlYUfC4O5P30s2tV SZgI7Lofv+lQwSLpMzqVjIny6TfkA7tgIas4WqxJVXYz96JGYpvv8AfLGcvfNWM= X-Google-Smtp-Source: AGHT+IGrYJKauK6ZcJyKJz7JlCwCofgjda6+JxtqTQ2saoYuavom2kgtDdRJaPeiZoY+65A1na55Lg== X-Received: by 2002:a6b:7311:0:b0:7c8:4c27:810e with SMTP id e17-20020a6b7311000000b007c84c27810emr520564ioh.18.1711570483944; Wed, 27 Mar 2024 13:14:43 -0700 (PDT) Received: from [100.64.0.1] ([170.85.6.190]) by smtp.gmail.com with ESMTPSA id g8-20020a02b708000000b0047469b04c35sm3465108jam.65.2024.03.27.13.14.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 27 Mar 2024 13:14:43 -0700 (PDT) Message-ID: Date: Wed, 27 Mar 2024 15:14:41 -0500 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [External] [PATCH v6 05/13] riscv: Only send remote fences when some other CPU is online To: yunhui cui Cc: Palmer Dabbelt , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, Alexandre Ghiti , Jisheng Zhang References: <20240327045035.368512-1-samuel.holland@sifive.com> <20240327045035.368512-6-samuel.holland@sifive.com> Content-Language: en-US From: Samuel Holland In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hi Yunhui, On 2024-03-27 1:16 AM, yunhui cui wrote: > On Wed, Mar 27, 2024 at 12:50 PM Samuel Holland > wrote: >> >> If no other CPU is online, a local cache or TLB flush is sufficient. >> These checks can be constant-folded when SMP is disabled. >> >> Signed-off-by: Samuel Holland >> --- >> >> (no changes since v4) >> >> Changes in v4: >> - New patch for v4 >> >> arch/riscv/mm/cacheflush.c | 4 +++- >> arch/riscv/mm/tlbflush.c | 4 +++- >> 2 files changed, 6 insertions(+), 2 deletions(-) >> >> diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c >> index d76fc73e594b..f5be1fec8191 100644 >> --- a/arch/riscv/mm/cacheflush.c >> +++ b/arch/riscv/mm/cacheflush.c >> @@ -21,7 +21,9 @@ void flush_icache_all(void) >> { >> local_flush_icache_all(); >> >> - if (riscv_use_sbi_for_rfence()) >> + if (num_online_cpus() < 2) >> + return; >> + else if (riscv_use_sbi_for_rfence()) >> sbi_remote_fence_i(NULL); >> else >> on_each_cpu(ipi_remote_fence_i, NULL, 1); >> diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c >> index da821315d43e..0901aa47b58f 100644 >> --- a/arch/riscv/mm/tlbflush.c >> +++ b/arch/riscv/mm/tlbflush.c >> @@ -79,7 +79,9 @@ static void __ipi_flush_tlb_all(void *info) >> >> void flush_tlb_all(void) >> { >> - if (riscv_use_sbi_for_rfence()) >> + if (num_online_cpus() < 2) >> + local_flush_tlb_all(); >> + else if (riscv_use_sbi_for_rfence()) >> sbi_remote_sfence_vma_asid(NULL, 0, FLUSH_TLB_MAX_SIZE, FLUSH_TLB_NO_ASID); >> else >> on_each_cpu(__ipi_flush_tlb_all, NULL, 1); >> -- >> 2.43.1 >> > > From a perceptual point of view, the modification here is not > necessary. There is such logic in on_each_cpu(). Can you share your > test data? The logic in on_each_cpu() doesn't apply when riscv_use_sbi_for_rfence() is true, so we would make unnecessary SBI calls, and cannot be oppimized out when CONFIG_SMP=n. The cover letter includes benchmarks for a representative single-core system (D1). There was no measurable performance impact from this portion of the series on multi-core systems. If there are specific benchmarks you think I should run, please let me know. Regards, Samuel