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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODExMDA3NSBTYWx0ZWRfX1JuZ4KXd18x2 XUtFU45jdTiAcxAidtIxO9Y6nwAJSiWFtx/rubO8bjTYpMaRHu0LloG7WTpglJ8Qgb8jfjfwC6u moRvJPVjWmr6F7tIgbSw0CRghjqTA7nASdC62wNbzjxMv64nVf/MfecG7N5d6Yf4ZXF5/FYDeuq sXNEXFu3Sz1BVMugZPmm07bJzOcHz7kdNTiSyvgDTcanx9mJHPogwGxvREqrzPupsGqOrYI96Tp ACxgPr/y3H4pA61qzYBjp4O1nYPQIEzkZUSkYmaZgMto4dTTkcIWtM5VRDqUtCzrXfCtehoRUlp Lp1XPWxweTfuf1oL4thNgGzvo4idBuEEcc6/jV4rEht9PbJ7zk/EZMmgsmZikC3bSzclZnvfcum sloQVGh4 X-Authority-Analysis: v=2.4 cv=TLZFS0la c=1 sm=1 tr=0 ts=689b4de1 cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=KKAkSRfTAAAA:8 a=OjNCceoZ-5M9CiTWRqAA:9 a=QEXdDO2ut3YA:10 a=a_PwQJl-kcHnX1M80qC6:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: VZS7J_sCSSRQzhQJTWmeaJ3oZqKj2yQ3 X-Proofpoint-ORIG-GUID: VZS7J_sCSSRQzhQJTWmeaJ3oZqKj2yQ3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-12_07,2025-08-11_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 malwarescore=0 spamscore=0 priorityscore=1501 bulkscore=0 adultscore=0 impostorscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508110075 On 8/6/25 2:38 PM, Krzysztof Kozlowski wrote: > Add Iris video codec to SM8750 SoC, which comes with significantly > different powering up sequence than previous SM8650, thus different > clocks and resets. For consistency keep existing clock and clock-names > naming, so the list shares common part. > > Signed-off-by: Krzysztof Kozlowski > > --- [...] > + iris_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-240000000 { > + opp-hz = /bits/ 64 <240000000>; > + required-opps = <&rpmhpd_opp_low_svs_d1>, > + <&rpmhpd_opp_low_svs_d1>; > + }; > + > + opp-338000000 { > + opp-hz = /bits/ 64 <338000000>; > + required-opps = <&rpmhpd_opp_low_svs>, > + <&rpmhpd_opp_low_svs>; > + }; > + > + opp-420000000 { > + opp-hz = /bits/ 64 <420000000>; > + required-opps = <&rpmhpd_opp_svs>, > + <&rpmhpd_opp_svs>; > + }; > + > + opp-444000000 { > + opp-hz = /bits/ 64 <444000000>; > + required-opps = <&rpmhpd_opp_svs_l1>, > + <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-533333334 { > + opp-hz = /bits/ 64 <533333334>; > + required-opps = <&rpmhpd_opp_nom>, > + <&rpmhpd_opp_nom>; > + }; There's an additional OPP: 570 MHz @ NOM_L1 +Dmitry, Vikash, please make sure you're OK with the iommu entries the other properties look OK Konrad