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From: Joel Fernandes <joelagnelf@nvidia.com>
To: "Gary Guo" <gary@garyguo.net>, "Miguel Ojeda" <ojeda@kernel.org>,
	"Boqun Feng" <boqun@kernel.org>,
	"Björn Roy Baron" <bjorn3_gh@protonmail.com>,
	"Benno Lossin" <lossin@kernel.org>,
	"Andreas Hindborg" <a.hindborg@kernel.org>,
	"Alice Ryhl" <aliceryhl@google.com>,
	"Trevor Gross" <tmgross@umich.edu>,
	"Danilo Krummrich" <dakr@kernel.org>,
	"Will Deacon" <will@kernel.org>,
	"Peter Zijlstra" <peterz@infradead.org>,
	"Mark Rutland" <mark.rutland@arm.com>
Cc: Alan Stern <stern@rowland.harvard.edu>,
	Andrea Parri <parri.andrea@gmail.com>,
	Nicholas Piggin <npiggin@gmail.com>,
	David Howells <dhowells@redhat.com>,
	Jade Alglave <j.alglave@ucl.ac.uk>,
	Luc Maranget <luc.maranget@inria.fr>,
	"Paul E. McKenney" <paulmck@kernel.org>,
	Akira Yokosawa <akiyks@gmail.com>,
	Daniel Lustig <dlustig@nvidia.com>,
	rust-for-linux@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arch@vger.kernel.org, lkmm@lists.linux.dev,
	Alexandre Courbot <acourbot@nvidia.com>,
	John Hubbard <jhubbard@nvidia.com>, Timur Tabi <ttabi@nvidia.com>,
	Eliot Courtney <ecourtney@nvidia.com>,
	Alistair Popple <apopple@nvidia.com>
Subject: Re: [PATCH 2/3] rust: sync: generic memory barriers
Date: Mon, 6 Apr 2026 14:01:00 -0400	[thread overview]
Message-ID: <e430a8c1-2dbc-4433-a9fd-976740e275d5@nvidia.com> (raw)
In-Reply-To: <DHKDNVH3DGV5.TP0X6143JHG0@garyguo.net>



On 4/4/2026 8:43 AM, Gary Guo wrote:
> On Fri Apr 3, 2026 at 10:33 PM BST, Joel Fernandes wrote:
>>
>>
>> On 4/2/2026 8:07 PM, Gary Guo wrote:
>>> On Thu Apr 2, 2026 at 10:49 PM BST, Joel Fernandes wrote:
>>
>> [...]
>>
>>>> See also in Documentation/memory-barriers.txt, ACQUIRE and RELEASE are defined as being
>>>> tied to specific memory operations.
>>>
>>> That's what we have today, hence the implementation upgrades them to full memory
>>> barriers. But ACQUIRE and RELEASE orderings doesn't *need* to be tied to
>>> specific memory operations and they can still make conceptual sense as barriers.
>>>
>>> C11 memory model defines Acquire and Release fences, and it looks to me it's
>>> relatively easy to add it to LKMM. I was playing with Herd7 and I think I've got
>>> it working, see the attached diff.
>>>
>>> Another thing that I'd like to note is that in all architectures that we have
>>> today except ARM and PARISC, the smp_load_acquire and smp_store_release are
>>> actually implemented as READ_ONCE + ACQUIRE barrier and RELEASE barrier +
>>> WRITE_ONCE. I'm planning to propose C API and corresponding memory model change
>>> too, but I want to gather some more concrete numbers (the performance benefit of
>>> having dma_mb_acquire/dma_mb_release compared to full dma_mb) before proposing so.
>>>
>>> Note that marked dma_load_acquire/dma_store_release (and their mandatory
>>> versions) don't make too much sense, as AFAIK no architectures have instructions
>>> for them so you're implementing these as fence instructions anyway.
>>
>> Ah, so you're proposing new memory barrier types that don't exist anywhere
>> in the kernel yet. I thought you were just wrapping existing ones so it got
>> a bit confusing.
> 
> Well, I am not proposing new memory barrier types in this change, hence I
> mentioned that these are annotations about intention and documentation and not
> about their *semantics* currently. Perhaps I didn't phrase this clear enough?
> 
> How about change the wording in documentation like this:
> 
>     /// `Acquire` is a full memory barrier, but caller indicates that it only
>     /// uses it to provide LOAD->{LOAD,STORE} ordering. 
> 
> or do you think even that is too much?

You are conflating lots of terms here, a "full memory barrier" is much stronger,
has stronger cumulativity properties etc (even stronger than Acquire/Release).

And I do think it is too much, because you are using the name of existing memory
barrier types (Acquire/Release) with specific definition, but saying "This is an
acquire lets pretend its a full memory barrier".  So you are in effect defining
new types IMO.

> 
>>
>> My suggestion: fix the nova-core issue in patch 3 using dma_mb() directly,
>> without the new barrier types. Adding a new standalone release/acquire
>> fence semantic to the kernel is something that will need broad consensus
>> from the LKMM maintainers IMO, independent of this series. It's a bigger
>> conversation that could delay your nova bug fix.
> 
> Something like this?
> 
>     // TODO: Replace with `dma_mb(Release)` when it's available.
>     dma_mb(Full);
> 
> Or not even mentioning that? I really like the Acquire/Release because they
> serve themselves a documentation on why the barrier is there to exist.

Sure that's certainly better, once the Release stuff that you're sort of
re-defining is accepted by LKMM maintainers and others, it can be replaced for
sure. But I wouldn't even want to mention a comment until this type of
"Standalone Release" is something everyone (LKMM reviewers) agree with and is
upstream-bound.  Just split the patch series into "Bug fix" and "New memory
barrier things".

> 
> When I read a full barrier, I always need to think whether the code really
> relies on STORE->LOAD ordering or a weaker ordering that could be used.
> There's a conventional wisdom in userspace C/Rust where when you see seq_cst,
> 99% of the time it's wrong.
> 
>>
>> Once smp_mb_release() / smp_mb_acquire() (or the DMA equivalents) land
>> properly, updating nova to use them will be trivial. But the correctness of
>> the fix shouldn't depend on semantics that don't exist in the kernel yet,
>> even if they currently degrade to a full barrier.
>>
>> That said, I find the idea genuinely interesting, and thanks for keeping me
>> in the loop. Standalone acquire/release fences that are formally modeled in
>> LKMM and A-cumulative is interesting as you showed in the herd7 code. You
>> would want to update Documentation/memory-barriers.txt too.
> 
> Yeah, there're more works to do on changing the semantics, hence I want to limit
> this to not be about semantics.

My gut feeling is, by calling it a Release (something that already has specific
definition), the marketing of this is probably going to be one of any hurdles.
:) But I'm curious about the take of others on this thread.

thanks,

--
Joel Fernandes


  reply	other threads:[~2026-04-06 18:01 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-04-02 15:24 [PATCH 0/3] rust: more memory barriers bindings Gary Guo
2026-04-02 15:24 ` [PATCH 1/3] rust: sync: add helpers for mb, dma_mb and friends Gary Guo
2026-04-13  5:33   ` Eliot Courtney
2026-04-02 15:24 ` [PATCH 2/3] rust: sync: generic memory barriers Gary Guo
2026-04-02 21:49   ` Joel Fernandes
2026-04-03  0:07     ` Gary Guo
2026-04-03 21:33       ` Joel Fernandes
2026-04-04 12:43         ` Gary Guo
2026-04-06 18:01           ` Joel Fernandes [this message]
2026-04-02 15:24 ` [PATCH 3/3] gpu: nova-core: fix wrong use of barriers in GSP code Gary Guo
2026-04-02 21:56   ` Joel Fernandes
2026-04-02 21:59     ` Joel Fernandes
2026-04-04 13:02     ` Gary Guo
2026-04-06 18:18       ` Joel Fernandes
2026-04-13  5:33   ` Eliot Courtney
2026-04-13 11:13     ` Gary Guo

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