From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B4A12BEFFE for ; Tue, 27 Jan 2026 22:26:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.52 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769552769; cv=none; b=CtlUbo1Ppd10METz+Z6hN1Zl2pSMlalaBYsExYj4/DxZpPS9/YchtUlVraScMiIi6Xv8NUomtiIvV35i0s4o5fLTefBdvAx2ts4e4lbgcWrvtSF3X1xzWFgnGhN31aSk44od89j4yhMmAbUe2JYH0JqTeWlZZK7yDe3eXniaWPg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769552769; c=relaxed/simple; bh=tuSMukXJSbPnemxeOAyoCOFeYGwA9TAC3Ka4b2eHMPQ=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=O2o9plUNfp35UUJfmdp6cOJfw9GDaCudrXB/gpVB8b8MtbfBiTyQcwf+lPKAD0b68Y8n2dCyQbEhpSN9D1neHP/tx4BZWLf1BVpT9yOT66brkNYTbnKoU+xg/KiNhU8DAlDc3E/KkDzS8hBCo058O5jeaNDoO1qOYolsUNxEkmI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=Y+sMq+QE; arc=none smtp.client-ip=209.85.128.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Y+sMq+QE" Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-48039fdc8aeso33016595e9.3 for ; Tue, 27 Jan 2026 14:26:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769552766; x=1770157566; darn=vger.kernel.org; h=content-transfer-encoding:in-reply-to:content-language:from :references:cc:to:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=3V2tn2mHvRqtIreRC+Gc5m2OsCJCgqMxstJvF4HcVy0=; b=Y+sMq+QECAoGne7Gc9l7bd7b8Leh+mph7ybArv5MztU858+L5JghkA8oGB50FIuExV yQBQg5/7fiXvuxqVNOeUg5vtAleZtqnhxCqcPziBdGpVECTafLg3c3K1uPyzO082vQDh 1di/47yj6yAwelrOxXoJy05VbxuBP/niCB0lePqaHM48ZGuGgn2yVufBtfXSc9N6XeoC +XLCapGp4Q8V/r2apIrU1xOO1my35JgBPTvj+49qzvjUq0s2s21Y8pbcweQO5IlbNRCr 8cn73FQqglbC0KCsSg/ExhrOSem8Na4b2SfUl3dkHakDLuWtUjjACcZsLTROnpp4dpHM eqvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769552766; x=1770157566; h=content-transfer-encoding:in-reply-to:content-language:from :references:cc:to:subject:user-agent:mime-version:date:message-id :x-gm-gg:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=3V2tn2mHvRqtIreRC+Gc5m2OsCJCgqMxstJvF4HcVy0=; b=sUOx6+6GWX+WuvSQHMS4gwiynGYmVyWAAUJ/yQV6pSxaZhtNcpy7p23vAgRutcQdTu U3v8xxK/CJN/KSgB8+6x+Lerps0XsgJdOQAcm0u/BMsZd4qBPoBzGY85Qsu+ac1RlpUV ZZ6AY1i4xGm7WRjhZVl9rK+bKNmELW4uAuHTeVRATDCTr+pN9n/bYUS+httiwrV3MxhX GPssghn9rUS7dP1hlx7dV7sn6skGQUpEhhmYeGptDPGi/obnm9I59iRKkJs0w2aAm/ZG K187E9EUC0qrANck0ysDeestUkXCSF51mnuQ77tQ/AaO3JpA4AByKRVjGbUizhtanceZ jjhA== X-Forwarded-Encrypted: i=1; AJvYcCUEei6qcrQ1+TEl5vhrT9cQBSPo+pkIMwT3kftYDWSlz0JvYIeofIpzsyV/5KeM0FLrnM4tVZuAg1F86F8=@vger.kernel.org X-Gm-Message-State: AOJu0YxhAQxEdVHIz6MontTeEbMbB61YFPpnlsnqRW5Y9U4Z0iD6Ehx2 0gZGgGRWcKvsCrZKwh1CDW9JoUtku93qG+h8WHX33Okf2+TFcAVGBnl7T9BE6jlDTI0= X-Gm-Gg: AZuq6aJcNo+gujwVRQZyWWBBAcXhr+Dw8lM/9bEiCqYLBmJVN1WIGNNoyLj3BEBNn/5 /ytk3XUqqTUD6PPzn9KuwnvcbAafWvoPGaDMSdYUdvpQQl/PJ0QGfJ5vAOmrfBGrbtpgm+9pbOg TIWc2ezvI9w4UWLGMWCM2NAfczB9XnmFVeGUGDsDXk5SlSXSBPD0Teu4qg74LY8CoVDo3RpXVL1 Llqd/Q5GVerzRmsCAErIu105L86jNFyk9K59E0kRgKyz8OVwI8YXsUyL8v9DPMJfiXrjsgGrDUb V5Ip/aWX/APBB1OY7WZMnZjwpR4r/5Z3VEIZhCcxxvED/rLzlzlxse4dctzQC1hXf/N/Xh7LERl NFUL3DipJMOW/RUrhW8rtpG4WNSNMP4TdU6by+poiFcFncSFWHDo/YHmuaQ+BoMc4dQZukhiaDB vZCzn+rpR01h+0SRClmD2vkTJShOg6ypRPMg5VsoNFhbbNtMP/og/+ X-Received: by 2002:a05:600c:1c13:b0:477:7925:f7fb with SMTP id 5b1f17b1804b1-48069c26ad2mr51439765e9.10.1769552765787; Tue, 27 Jan 2026 14:26:05 -0800 (PST) Received: from [192.168.0.40] (188-141-3-146.dynamic.upc.ie. [188.141.3.146]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4806cdeafffsm19705125e9.7.2026.01.27.14.26.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 27 Jan 2026 14:26:05 -0800 (PST) Message-ID: Date: Tue, 27 Jan 2026 22:26:03 +0000 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/8] clk: qcom: camcc-x1e80100: Add support for camera QDSS debug clocks To: Jagadeesh Kona , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jagadeesh Kona , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Taniya Das , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260128-purwa-videocc-camcc-v1-0-b23de57df5ba@oss.qualcomm.com> <20260128-purwa-videocc-camcc-v1-4-b23de57df5ba@oss.qualcomm.com> From: Bryan O'Donoghue Content-Language: en-US In-Reply-To: <20260128-purwa-videocc-camcc-v1-4-b23de57df5ba@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 27/01/2026 19:26, Jagadeesh Kona wrote: > Add support for camera QDSS debug clocks on X1E80100 platform. > A little more detail here please :) > Signed-off-by: Jagadeesh Kona > --- > drivers/clk/qcom/camcc-x1e80100.c | 64 +++++++++++++++++++++++++++++++++++++++ > 1 file changed, 64 insertions(+) > > diff --git a/drivers/clk/qcom/camcc-x1e80100.c b/drivers/clk/qcom/camcc-x1e80100.c > index cbcc1c9fcb341e51272f5595f574f9cb7ef2b52e..7e3fc7aee854eee841176a1330f97dc91af91670 100644 > --- a/drivers/clk/qcom/camcc-x1e80100.c > +++ b/drivers/clk/qcom/camcc-x1e80100.c > @@ -1052,6 +1052,31 @@ static struct clk_rcg2 cam_cc_mclk7_clk_src = { > }, > }; > > +static const struct freq_tbl ftbl_cam_cc_qdss_debug_clk_src[] = { > + F(19200000, P_BI_TCXO, 1, 0, 0), > + F(60000000, P_CAM_CC_PLL8_OUT_EVEN, 8, 0, 0), > + F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0), > + F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0), > + F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 cam_cc_qdss_debug_clk_src = { > + .cmd_rcgr = 0x13938, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = cam_cc_parent_map_0, > + .freq_tbl = ftbl_cam_cc_qdss_debug_clk_src, > + .hw_clk_ctrl = true, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_qdss_debug_clk_src", > + .parent_data = cam_cc_parent_data_0, > + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > static const struct freq_tbl ftbl_cam_cc_sfe_0_clk_src[] = { > F(345600000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), > F(432000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), > @@ -2182,6 +2207,42 @@ static struct clk_branch cam_cc_mclk7_clk = { > }, > }; > > +static struct clk_branch cam_cc_qdss_debug_clk = { > + .halt_reg = 0x13a64, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x13a64, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_qdss_debug_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_qdss_debug_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch cam_cc_qdss_debug_xo_clk = { > + .halt_reg = 0x13a68, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x13a68, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_qdss_debug_xo_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_xo_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > static struct clk_branch cam_cc_sfe_0_clk = { > .halt_reg = 0x133c0, > .halt_check = BRANCH_HALT, > @@ -2398,6 +2459,9 @@ static struct clk_regmap *cam_cc_x1e80100_clocks[] = { > [CAM_CC_PLL6_OUT_EVEN] = &cam_cc_pll6_out_even.clkr, > [CAM_CC_PLL8] = &cam_cc_pll8.clkr, > [CAM_CC_PLL8_OUT_EVEN] = &cam_cc_pll8_out_even.clkr, > + [CAM_CC_QDSS_DEBUG_CLK] = &cam_cc_qdss_debug_clk.clkr, > + [CAM_CC_QDSS_DEBUG_CLK_SRC] = &cam_cc_qdss_debug_clk_src.clkr, > + [CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr, > [CAM_CC_SFE_0_CLK] = &cam_cc_sfe_0_clk.clkr, > [CAM_CC_SFE_0_CLK_SRC] = &cam_cc_sfe_0_clk_src.clkr, > [CAM_CC_SFE_0_FAST_AHB_CLK] = &cam_cc_sfe_0_fast_ahb_clk.clkr, > Once the commit log is fixed. Reviewed-by: Bryan O'Donoghue --- bod