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charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.2-0+deb13u1 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 On Mi, 2026-11-04 at 02:21 -0500, Joseph Telaak via B4 Relay wrote: > From: Chuanhong Guo >=20 > Add a platform driver for the peripheral clock and reset manager (CRM) > block found on Siflower SF19A2890 and compatible SoCs. >=20 > Each CRM block manages a group of APB peripherals through three registers= : > a reset register, a clock gate register, and a shared Bus Output Enable > (BOE) register that must be asserted for any peripheral in the block to > respond to bus transactions. >=20 > The driver registers a clock gate controller and a reset controller from > a single DT node. A shared spinlock protects all read-modify-write > accesses across both. BOE is managed automatically: asserted when the > first clock gate is enabled and deasserted when the last one is disabled. >=20 > Signed-off-by: Chuanhong Guo > [jt: from Chuanhong's siflower-7.1 branch; one compatible per block with > its gate bits, critical gates and reset masks in tables here instead of > the siflower,valid-gates, siflower,critical-gates, siflower,reset-masks > and siflower,num-resets properties, gate N parented to input clock N by > index instead of by global name, the gate updates under the spinlock too= , > no separator comments, Kconfig dependencies and help, subject] > Signed-off-by: Joseph Telaak > --- > drivers/clk/siflower/Kconfig | 11 + > drivers/clk/siflower/Makefile | 1 + > drivers/clk/siflower/clk-sf19a2890-periphcrm.c | 360 +++++++++++++++++++= ++++++ > 3 files changed, 372 insertions(+) >=20 [...] > diff --git a/drivers/clk/siflower/clk-sf19a2890-periphcrm.c b/drivers/clk= /siflower/clk-sf19a2890-periphcrm.c > new file mode 100644 > index 000000000..95d4dd449 > --- /dev/null > +++ b/drivers/clk/siflower/clk-sf19a2890-periphcrm.c > @@ -0,0 +1,360 @@ [...] > +#define CRM_DATA(_g, _r) \ > + { \ > + .gates =3D sf19a2890_##_g##_gates, \ > + .num_gates =3D ARRAY_SIZE(sf19a2890_##_g##_gates), \ > + .reset_masks =3D sf19a2890_##_r##_resets, \ > + .num_resets =3D ARRAY_SIZE(sf19a2890_##_r##_resets), \ > + } > + > +static const u32 sf19a2890_single_resets[] =3D { BIT(0) }; > + [...] > + > +static const u32 sf19a2890_gmac_resets[] =3D { GENMASK(1, 0) }; Are these two bits separate resets? Are they individually controllable? Why are they bundled into a single reset_control like this? The commit message doesn't explain. [...] > +static const u32 sf19a2890_wlan_resets[] =3D { GENMASK(2, 0) }; [...] > +static const u32 sf19a2890_usb_resets[] =3D { GENMASK(2, 0), BIT(3), BIT= (4) }; [...] > +static const u32 sf19a2890_spi_resets[] =3D { GENMASK(5, 4) }; [...] > +static const u32 sf19a2890_uart_resets[] =3D { > + BIT(0) | BIT(4), BIT(1) | BIT(5), BIT(2) | BIT(6), > +}; Same question for the other multi-bit masks. regards Philipp