From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 261A7C433EF for ; Fri, 25 Feb 2022 02:18:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236737AbiBYCTO (ORCPT ); Thu, 24 Feb 2022 21:19:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59756 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229794AbiBYCTK (ORCPT ); Thu, 24 Feb 2022 21:19:10 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1EFEB1201B9 for ; Thu, 24 Feb 2022 18:18:38 -0800 (PST) X-UUID: c27ce0157a1b41458026002c52152178-20220225 X-UUID: c27ce0157a1b41458026002c52152178-20220225 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1880850522; Fri, 25 Feb 2022 10:18:35 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Fri, 25 Feb 2022 10:18:34 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 25 Feb 2022 10:18:34 +0800 Message-ID: Subject: Re: [3/3] drm/mediatek: keep dsi as LP00 before dcs cmds transfer From: CK Hu To: , , , , , CC: , , , , , , Jitao Shi Date: Fri, 25 Feb 2022 10:18:34 +0800 In-Reply-To: <1644589818-13066-4-git-send-email-xinlei.lee@mediatek.com> References: <1644589818-13066-1-git-send-email-xinlei.lee@mediatek.com> <1644589818-13066-4-git-send-email-xinlei.lee@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Xinlei: On Fri, 2022-02-11 at 22:30 +0800, xinlei.lee@mediatek.com wrote: > From: Jitao Shi > > To comply with the panel sequence, hold the mipi signal to LP00 > before the dcs cmds transmission, > and pull the mipi signal high from LP00 to LP11 until the start of > the dcs cmds transmission. > If dsi is not in cmd mode, then dsi will pull the mipi signal high in > the mtk_output_dsi_enable function. > > Signed-off-by: Jitao Shi > Signed-off-by: Xinlei Lee > --- > drivers/gpu/drm/mediatek/mtk_dsi.c | 32 +++++++++++++++++++++++++--- > ---- > 1 file changed, 25 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c > b/drivers/gpu/drm/mediatek/mtk_dsi.c > index e47c338..17a5270 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c > @@ -203,6 +203,7 @@ struct mtk_dsi { > struct mtk_phy_timing phy_timing; > int refcount; > bool enabled; > + bool lanes_ready; > u32 irq_data; > wait_queue_head_t irq_wait_queue; > const struct mtk_dsi_driver_data *driver_data; > @@ -654,13 +655,6 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) > mtk_dsi_config_vdo_timing(dsi); > mtk_dsi_set_interrupt_enable(dsi); > > - mtk_dsi_rxtx_control(dsi); > - usleep_range(30, 100); > - mtk_dsi_reset_dphy(dsi); > - mtk_dsi_clk_ulp_mode_leave(dsi); > - mtk_dsi_lane0_ulp_mode_leave(dsi); > - mtk_dsi_clk_hs_mode(dsi, 0); > - > return 0; > err_disable_engine_clk: > clk_disable_unprepare(dsi->engine_clk); > @@ -682,6 +676,8 @@ static void mtk_dsi_poweroff(struct mtk_dsi *dsi) > mtk_dsi_reset_engine(dsi); > mtk_dsi_lane0_ulp_mode_enter(dsi); > mtk_dsi_clk_ulp_mode_enter(dsi); > + /* set the lane number as 0 */ > + writel(0, dsi->regs + DSI_TXRX_CTRL); If this is not related to 'sequence', separate this to another patch. Regards, CK > > mtk_dsi_disable(dsi); > > @@ -689,6 +685,8 @@ static void mtk_dsi_poweroff(struct mtk_dsi *dsi) > clk_disable_unprepare(dsi->digital_clk); > > phy_power_off(dsi->phy); > + > + dsi->lanes_ready = false; > } > > static void mtk_output_dsi_enable(struct mtk_dsi *dsi) > @@ -696,6 +694,16 @@ static void mtk_output_dsi_enable(struct mtk_dsi > *dsi) > if (dsi->enabled) > return; > > + if (!dsi->lanes_ready) { > + dsi->lanes_ready = true; > + mtk_dsi_rxtx_control(dsi); > + usleep_range(30, 100); > + mtk_dsi_reset_dphy(dsi); > + mtk_dsi_clk_ulp_mode_leave(dsi); > + mtk_dsi_lane0_ulp_mode_leave(dsi); > + mtk_dsi_clk_hs_mode(dsi, 0); > + } > + > mtk_dsi_set_mode(dsi); > mtk_dsi_clk_hs_mode(dsi, 1); > > @@ -907,6 +915,16 @@ static ssize_t mtk_dsi_host_transfer(struct > mipi_dsi_host *host, > if (MTK_DSI_HOST_IS_READ(msg->type)) > irq_flag |= LPRX_RD_RDY_INT_FLAG; > > + if (!dsi->lanes_ready) { > + dsi->lanes_ready = true; > + mtk_dsi_rxtx_control(dsi); > + usleep_range(30, 100); > + mtk_dsi_reset_dphy(dsi); > + mtk_dsi_clk_ulp_mode_leave(dsi); > + mtk_dsi_lane0_ulp_mode_leave(dsi); > + mtk_dsi_clk_hs_mode(dsi, 0); > + msleep(20); > + } > if (mtk_dsi_host_send_cmd(dsi, msg, irq_flag) < 0) > return -ETIME; >