From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
To: Hsiao Chien Sung <shawn.sung@mediatek.com>,
Chun-Kuang Hu <chunkuang.hu@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org,
Project_Global_Chrome_Upstream_Group@mediatek.com,
Singo Chang <singo.chang@mediatek.com>,
Nancy Lin <nancy.lin@mediatek.com>,
Jason-JH Lin <jason-jh.lin@mediatek.com>
Subject: Re: [PATCH v2 12/15] soc: mediatek: Add MT8188 VDO1 reset bit map
Date: Wed, 14 Jun 2023 13:35:23 +0200 [thread overview]
Message-ID: <e4f98dc5-0fa6-14aa-f8d0-e4bf30ecca5c@collabora.com> (raw)
In-Reply-To: <20230614073125.17958-13-shawn.sung@mediatek.com>
Il 14/06/23 09:31, Hsiao Chien Sung ha scritto:
> Add MT8188 VDO1 reset bit map.
>
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
> drivers/soc/mediatek/mt8188-mmsys.h | 57 +++++++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.c | 3 +-
> 2 files changed, 59 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/soc/mediatek/mt8188-mmsys.h b/drivers/soc/mediatek/mt8188-mmsys.h
> index c3e3c5cfe931..208d4dfedc1a 100644
> --- a/drivers/soc/mediatek/mt8188-mmsys.h
> +++ b/drivers/soc/mediatek/mt8188-mmsys.h
> @@ -144,6 +144,63 @@ static const u8 mmsys_mt8188_vdo0_rst_tb[] = {
> [MT8188_VDO0_RST_DISP_RSZ0] = 31,
> };
>
> +static const u8 mmsys_mt8188_vdo1_rst_tb[] = {
> + [MT8188_VDO1_RST_SMI_LARB2] = 0,
> + [MT8188_VDO1_RST_SMI_LARB3] = 1,
> + [MT8188_VDO1_RST_GALS] = 2,
> + [MT8188_VDO1_RST_FAKE_ENG0] = 3,
> + [MT8188_VDO1_RST_FAKE_ENG1] = 4,
> + [MT8188_VDO1_RST_MDP_RDMA0] = 5,
> + [MT8188_VDO1_RST_MDP_RDMA1] = 6,
> + [MT8188_VDO1_RST_MDP_RDMA2] = 7,
> + [MT8188_VDO1_RST_MDP_RDMA3] = 8,
> + [MT8188_VDO1_RST_VPP_MERGE0] = 9,
> + [MT8188_VDO1_RST_VPP_MERGE1] = 10,
> + [MT8188_VDO1_RST_VPP_MERGE2] = 11,
> + [MT8188_VDO1_RST_VPP_MERGE3] = 32 + 0,
Works, but there's a better way.
32 + 0 means that you're using reset SW1 register, so you can do
#define MT8188_MMSYS_RST_NR_PER_BANK 32
#define MT8188_RST_SW1_OFFSET MT8188_MMSYS_RST_NR_PER_BANK
#define MT8188_RST_SW2_OFFSET MT8188_MMSYS_RST_NR_PER_BANK * 2
[MT8188_VDO1_RST_VPP_MERGE3] = MT8188_RST_SW1_OFFSET + 0
[MT8188_VDO1_RST_VPP_MERGE4] = MT8188_RST_SW1_OFFSET + 0
.......
[MT8188_VDO1_RST_HDR_VDO_FE0] = MT8188_RST_SW2_OFFSET + 0
...etc
Reading this will make it clear that a certain reset bit is in a different
(sequential or not) register.
P.S.: If the RST_NR_PER_BANK is *not* MT8188 specific (as in, all reset registers
for all SoCs are always 32 bits, which I believe is true), you could move that
definition to mtk-mmsys.h as
#define MMSYS_RST_NR_PER_BANK 32
and then define the offsets in mt8188-mmsys.h as
#define MT8188_RST_SW1_OFFSET MMSYS_RST_NR_PER_BANK
.... etc
Thanks,
Angelo
next prev parent reply other threads:[~2023-06-14 11:35 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-14 7:31 [PATCH v2 00/15] Add display driver for MT8188 VDOSYS1 Hsiao Chien Sung
2023-06-14 7:31 ` [PATCH v2 01/15] dt-bindings: display: mediatek: ethdr: Add compatible for MT8188 Hsiao Chien Sung
2023-06-14 11:41 ` AngeloGioacchino Del Regno
2023-06-15 5:51 ` Shawn Sung (宋孝謙)
2023-06-15 7:36 ` AngeloGioacchino Del Regno
2023-06-15 8:24 ` Krzysztof Kozlowski
2023-06-14 7:31 ` [PATCH v2 02/15] dt-bindings: display: mediatek: mdp-rdma: " Hsiao Chien Sung
2023-06-14 11:41 ` AngeloGioacchino Del Regno
2023-06-15 8:33 ` Krzysztof Kozlowski
2023-06-14 7:31 ` [PATCH v2 03/15] dt-bindings: display: mediatek: merge: " Hsiao Chien Sung
2023-06-14 11:41 ` AngeloGioacchino Del Regno
2023-06-15 8:28 ` Krzysztof Kozlowski
2023-06-16 5:29 ` Shawn Sung (宋孝謙)
2023-06-16 8:07 ` Krzysztof Kozlowski
2023-06-16 8:40 ` Shawn Sung (宋孝謙)
2023-06-16 9:31 ` Krzysztof Kozlowski
2023-06-16 11:51 ` Shawn Sung (宋孝謙)
2023-06-14 7:31 ` [PATCH v2 04/15] dt-bindings: display: mediatek: padding: Add documentation " Hsiao Chien Sung
2023-06-15 8:32 ` Krzysztof Kozlowski
2023-06-16 5:40 ` Shawn Sung (宋孝謙)
2023-06-14 7:31 ` [PATCH v2 05/15] dt-bindings: arm: mediatek: Add compatible " Hsiao Chien Sung
2023-06-14 11:42 ` AngeloGioacchino Del Regno
2023-06-15 8:33 ` Krzysztof Kozlowski
2023-06-14 7:31 ` [PATCH v2 06/15] dt-bindings: reset: mt8188: Add VDOSYS0 reset control bits Hsiao Chien Sung
2023-06-14 11:27 ` AngeloGioacchino Del Regno
2023-06-22 1:42 ` Rob Herring
2023-06-27 6:52 ` Shawn Sung (宋孝謙)
2023-06-14 7:31 ` [PATCH v2 07/15] dt-bindings: reset: mt8188: Add VDOSYS1 " Hsiao Chien Sung
2023-06-14 11:27 ` AngeloGioacchino Del Regno
2023-06-15 8:34 ` Krzysztof Kozlowski
2023-06-14 7:31 ` [PATCH v2 08/15] soc: mediatek: Support MT8188 VDOSYS1 in mtk-mmsys Hsiao Chien Sung
2023-06-14 11:21 ` AngeloGioacchino Del Regno
2023-06-15 6:10 ` Shawn Sung (宋孝謙)
2023-06-15 7:38 ` AngeloGioacchino Del Regno
2023-06-14 7:31 ` [PATCH v2 09/15] soc: mediatek: Support MT8188 VDOSYS1 PADDING " Hsiao Chien Sung
2023-06-14 11:22 ` AngeloGioacchino Del Regno
2023-06-14 7:31 ` [PATCH v2 10/15] soc: mediatek: Support reset bit mapping in mmsys driver Hsiao Chien Sung
2023-06-14 11:28 ` AngeloGioacchino Del Regno
2023-06-14 7:31 ` [PATCH v2 11/15] soc: mediatek: Add MT8188 VDO0 reset bit map Hsiao Chien Sung
2023-06-14 11:29 ` AngeloGioacchino Del Regno
2023-06-14 7:31 ` [PATCH v2 12/15] soc: mediatek: Add MT8188 VDO1 " Hsiao Chien Sung
2023-06-14 11:35 ` AngeloGioacchino Del Regno [this message]
2023-06-15 6:01 ` Shawn Sung (宋孝謙)
2023-06-15 7:37 ` AngeloGioacchino Del Regno
2023-06-14 7:31 ` [PATCH v2 13/15] drm/mediatek: Support MT8188 VDOSYS1 in display driver Hsiao Chien Sung
2023-06-14 11:37 ` AngeloGioacchino Del Regno
2023-06-14 7:31 ` [PATCH v2 14/15] drm/mediatek: Improve compatibility of " Hsiao Chien Sung
2023-06-14 7:31 ` [PATCH v2 15/15] drm/mediatek: Support MT8188 VDOSYS1 PADDING in " Hsiao Chien Sung
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