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[77.136.154.89]) by smtp.googlemail.com with ESMTPSA id v192-v6sm14197856wmf.40.2018.09.23.22.58.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 23 Sep 2018 22:58:44 -0700 (PDT) Subject: Re: [PATCH v7 05/24] clocksource: Add a new timer-ingenic driver To: Paul Cercueil Cc: Mathieu Malaterre , Thomas Gleixner , Rob Herring , linux-doc@vger.kernel.org, Jonathan Corbet , linux-watchdog@vger.kernel.org, od@zcrc.me, linux-mips@linux-mips.org, Paul Burton , Mark Rutland , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Ralf Baechle , Thierry Reding , linux-pwm@vger.kernel.org References: <5ba87b02.1c69fb81.1da88.1457SMTPIN_ADDED_MISSING@mx.google.com> From: Daniel Lezcano Message-ID: Date: Mon, 24 Sep 2018 07:58:42 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: <5ba87b02.1c69fb81.1da88.1457SMTPIN_ADDED_MISSING@mx.google.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 24/09/2018 07:49, Paul Cercueil wrote: > > Le 24 sept. 2018 07:35, Daniel Lezcano a > écrit : >> >> On 24/09/2018 07:24, Paul Cercueil wrote: >>> Hi Daniel, >>> >>> Le 24 sept. 2018 05:12, Daniel Lezcano >>> a écrit : >>>> >>>> On 21/08/2018 19:16, Paul Cercueil wrote: >>>>> This driver handles the TCU (Timer Counter Unit) present on >>>>> the Ingenic JZ47xx SoCs, and provides the kernel with a >>>>> system timer, and optionally with a clocksource and a >>>>> sched_clock. >>>>> >>>>> It also provides clocks and interrupt handling to client >>>>> drivers. >>>> >>>> Can you provide a much more complete description of the timer >>>> in order to make my life easier for the review of this patch? >>> >>> See patch [03/24], it adds a doc file that describes the >>> hardware. >> >> Thanks, I went through but it is incomplete to understand what the >> timer do. I will reverse-engineer the code but it would help if you >> can give the gross approach. Why multiple channels ? mutexes and >> completion ? > > Much of the complexity is because of the multi-purpose nature of the > TCU channels. Each one can be used as timer/clocksource, or PWM. > > The driver starts by using channels 0 and 1 as system timer and > clocksource, respectively, the other ones being unused for now. Then, > *if* the PWM driver requests one of the channels in use by the > timer/clocksource driver, say channel 0, the timer/clocksource driver > will dynamically reassign the system timer to a free channel, from > channel 0 to e.g. channel 2. Only in that case the completion/mutex > are actually used. Why do you need to do this? Can't be the channels dedicated and reserved for clocksource and clockevent? -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog