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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-774662f9cfdsm853480b3a.101.2025.09.08.23.10.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 08 Sep 2025 23:10:37 -0700 (PDT) Message-ID: Date: Tue, 9 Sep 2025 14:10:34 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 0/4] PCI: qcom: Add support for Glymur PCIe Gen5x4 To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Bjorn Helgaas , Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, konrad.dybcio@oss.qualcomm.com, qiang.yu@oss.qualcomm.com, Prudhvi Yarlagadda , Dmitry Baryshkov References: <20250903-glymur_pcie5-v4-0-c187c2d9d3bd@oss.qualcomm.com> Content-Language: en-US From: "Wenbin Yao (Consultant)" In-Reply-To: <20250903-glymur_pcie5-v4-0-c187c2d9d3bd@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: iffpjMzD7vMR90T1UIrJi6jNADA006n2 X-Proofpoint-GUID: iffpjMzD7vMR90T1UIrJi6jNADA006n2 X-Authority-Analysis: v=2.4 cv=NdLm13D4 c=1 sm=1 tr=0 ts=68bfc4df cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=nBUzdE8Pax3goPOuR84A:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA4MDA2NiBTYWx0ZWRfXxCAhQtw9Yy+k xPV6kitEvqZ8OTpMV1takP3PGRXUIf5+F5MuiXHFuQp9XQVpupuI7jCr/nk3aTYVEU5wdNNpmHn fdJna52DPGoF7TpzDbSt14kqAl1eDsHR9+Y2i/6bhJzb0rPuOPVVaqD28spS96Dh1dDzimpeDon Llz2QeH1t5mdq1rWpRS39IqGWS7Kdy3yLnZkeH9n88XtkxN0aUaM1WNwcsE8T4OV6a+XPGuhI2A WinfW5kupZGMAtxDhkkNIbd4n+1GuXC4BOzPqstnsB5X966niorxVIdXl+6a/qoFrjJI4T2H05R K+tdhlNG/77SmGkWSWCqmPHUCR4LhTHR547Sho5hR+5yvYE4+Q62xn13nJ2X0+YGgcJbosZe7nu QCwDYJzJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-08_06,2025-09-08_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 adultscore=0 suspectscore=0 phishscore=0 clxscore=1015 impostorscore=0 spamscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509080066 On 9/4/2025 2:22 PM, Wenbin Yao wrote: > Glymur is the next generation compute SoC of Qualcomm. This patch series > aims to add support for the fifth PCIe instance on it. The fifth PCIe > instance on Glymur has a Gen5 4-lane PHY. Patch [1/4] documents PHY as a > separate compatible and Patch [2/4] documents controller as a separate > compatible. Patch [3/4] describles the new PCS offsets in a dedicated > header file. Patch [4/4] adds configuration and compatible for PHY. > > The device tree changes and whatever driver patches that are not part of > this patch series will be posted separately after official announcement of > the SOC. > > Signed-off-by: Wenbin Yao > --- > Changes in v4: > - Rebase Patch[1/4] onto next branch of linux-phy. > - Rebase Patch[4/4] onto next branch of linux-phy. > - Link to v3: https://lore.kernel.org/r/20250825-glymur_pcie5-v3-0-5c1d1730c16f@oss.qualcomm.com > > Changes in v3: > - Keep qmp_pcie_of_match_table array sorted. > - Drop qref supply for PCIe Gen5x4 PHY. > - Link to v2: https://lore.kernel.org/r/20250821-glymur_pcie5-v2-0-cd516784ef20@oss.qualcomm.com > > Changes in v2: > - Add offsets of PLL and TXRXZ register blocks for v8.50 PHY in Patch[4/4]. > - Link to v1: https://lore.kernel.org/r/20250819-glymur_pcie5-v1-0-2ea09f83cbb0@oss.qualcomm.com > > --- > Prudhvi Yarlagadda (4): > dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the Glymur QMP PCIe PHY > dt-bindings: PCI: qcom: Document the Glymur PCIe Controller > phy: qcom-qmp: pcs: Add v8.50 register offsets > phy: qcom: qmp-pcie: Add support for Glymur PCIe Gen5x4 PHY > > .../bindings/pci/qcom,pcie-x1e80100.yaml | 7 ++++- > .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 3 ++ > drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 32 ++++++++++++++++++++++ > drivers/phy/qualcomm/phy-qcom-qmp-pcs-v8_50.h | 13 +++++++++ > drivers/phy/qualcomm/phy-qcom-qmp.h | 2 ++ > 5 files changed, 56 insertions(+), 1 deletion(-) > --- > base-commit: 356590cd61cf89e2420d5628e35b6e73c6b6a770 > change-id: 20250902-glymur_pcie5-bec675b7bdba > > Best regards, Hello, do you have any futher comments? -- With best wishes Wenbin