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Mon, 23 Feb 2026 21:21:15 -0800 (PST) X-Received: by 2002:a05:6a00:1150:b0:824:374a:1404 with SMTP id d2e1a72fcca58-826daa9425bmr10111794b3a.46.1771910475526; Mon, 23 Feb 2026 21:21:15 -0800 (PST) Received: from [10.218.35.45] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-826dd8cbb02sm9512889b3a.57.2026.02.23.21.21.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 23 Feb 2026 21:21:15 -0800 (PST) Message-ID: Date: Tue, 24 Feb 2026 10:51:10 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/3] PCI/ASPM: Add helper to encode L1SS T_POWER_ON fields To: Bjorn Helgaas Cc: Manivannan Sadhasivam , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Jingoo Han , linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, mayank.rana@oss.qualcomm.com, quic_vbadigan@quicinc.com References: <20260223152901.GA3694918@bhelgaas> Content-Language: en-US From: Krishna Chaitanya Chundru In-Reply-To: <20260223152901.GA3694918@bhelgaas> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: 2mQhOgyn-xdO8n0UBP46UXT7ZQTqEXPS X-Authority-Analysis: v=2.4 cv=V7twEOni c=1 sm=1 tr=0 ts=699d354c cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=kJBpcOZ6olZWUerAqwAA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjI0MDA0MyBTYWx0ZWRfX17vRW5L3fnf3 J/IV3F4PDFXGXvSLjBI16rsAfjOmCetmZyXg51zX5Ydhk2CxmwdlFEzxzJhec17V0YZiWSyXea/ bw0iqn22NkRwg79ENgIjmrdEoYJYwWAtpydI5hdFiGmSaI6N2mI2rYmJVebX8DIGpgzr3Uxo8YZ Q2kfoZ8nNBKRYa/WEaOBF1uBmQgcwOxCZOe6I+1VrNHjf82nUeMFpmoSNtNJqInfsBzAtbJO1M4 njpSo+00+cSlDdIW5mcI6rHzf85z2pAXK7gnGQWVCvOWehDuDWfifoarBvJltqX5Fd7ZaZ7U3yb bCLC4Tgo99TD6yx9F8ctwHbb4tTTWOH6Uui43SNlJPtVbNEcWJRTBE5F80wtk+q6b4OYjCbfpSC 0N9ZuLS5c5vM+zpijKkisaVAI3kQwlaMO1uWnYDAlTow1dCEz+4mtsRNzEa78Rh2KX/jTdblJtF YugXL3HweuQLBboXk5w== X-Proofpoint-GUID: 2mQhOgyn-xdO8n0UBP46UXT7ZQTqEXPS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-23_06,2026-02-23_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 lowpriorityscore=0 suspectscore=0 phishscore=0 impostorscore=0 bulkscore=0 priorityscore=1501 malwarescore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2602240043 On 2/23/2026 8:59 PM, Bjorn Helgaas wrote: > On Mon, Feb 23, 2026 at 04:43:30PM +0530, Krishna Chaitanya Chundru wrote: >> Add a shared helper to encode the PCIe L1 PM Substates T_POWER_ON >> parameter into the T_POWER_ON_Scale and T_POWER_ON_Value fields. >> >> This helper can be used by the controller drivers to change the >> default/wrong value of T_POWER_ON in L1ss capability register to >> avoid incorrect calculation of LTR_L1.2_THRESHOLD value. >> >> The helper converts a T_POWER_ON time specified in microseconds into >> the appropriate scale/value encoding defined by the PCIe spec r7.0, >> sec 7.8.3.2. Values that exceed the maximum encodable range are clamped >> to the largest representable encoding. >> >> Signed-off-by: Krishna Chaitanya Chundru >> --- >> drivers/pci/pcie/aspm.c | 43 +++++++++++++++++++++++++++++++++++++++++++ >> include/linux/pci.h | 2 ++ >> 2 files changed, 45 insertions(+) >> >> diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c >> index 21f5d23e0b61bd7e1163cc869fe9356d1ab87b34..d7f9ae9e48c25dbc2d9b4887e2f74623688098e0 100644 >> --- a/drivers/pci/pcie/aspm.c >> +++ b/drivers/pci/pcie/aspm.c >> @@ -525,6 +525,49 @@ static u32 calc_l12_pwron(struct pci_dev *pdev, u32 scale, u32 val) >> return 0; >> } >> >> +/** >> + * pcie_encode_t_power_on - Encode T_POWER_ON into scale and value fields >> + * @t_power_on_us: T_POWER_ON time in microseconds >> + * @scale: Encoded T_POWER_ON_Scale (0..2) >> + * @value: Encoded T_POWER_ON_Value >> + * >> + * T_POWER_ON is encoded as: >> + * T_POWER_ON(us) = scale_unit(us) * value >> + * >> + * where scale_unit is selected by @scale: >> + * 0: 2us >> + * 1: 10us >> + * 2: 100us >> + * >> + * If @t_power_on_us exceeds the maximum representable value, the result >> + * is clamped to the largest encodable T_POWER_ON. >> + * >> + * See PCIe r7.0, sec 7.8.3.2. >> + */ >> +void pcie_encode_t_power_on(u16 t_power_on_us, u8 *scale, u8 *value) >> +{ >> + u8 maxv = FIELD_MAX(PCI_L1SS_CTL2_T_PWR_ON_VALUE); >> + >> + /* >> + * T_POWER_ON_Value ("value") is a 5-bit field with max >> + * value of 31. >> + */ >> + if (t_power_on_us <= 2 * maxv) { >> + *scale = 0; /* Value times 2us */ >> + *value = DIV_ROUND_UP(t_power_on_us, 2); >> + } else if (t_power_on_us <= 10 * maxv) { >> + *scale = 1; /* Value times 10us */ >> + *value = DIV_ROUND_UP(t_power_on_us, 10); >> + } else if (t_power_on_us <= 100 * maxv) { >> + *scale = 2; /* value times 100us */ >> + *value = DIV_ROUND_UP(t_power_on_us, 100); >> + } else { >> + *scale = 2; >> + *value = maxv; >> + } >> +} >> +EXPORT_SYMBOL(pcie_encode_t_power_on); >> + >> /* >> * Encode an LTR_L1.2_THRESHOLD value for the L1 PM Substates Control 1 >> * register. Ports enter L1.2 when the most recent LTR value is greater >> diff --git a/include/linux/pci.h b/include/linux/pci.h >> index 1c270f1d512301de4d462fe7e5097c32af5c6f8d..eec16fdcb9996ab0f663f4587a2367a676a49ce6 100644 >> --- a/include/linux/pci.h >> +++ b/include/linux/pci.h >> @@ -1911,6 +1911,7 @@ int pci_enable_link_state_locked(struct pci_dev *pdev, int state); >> void pcie_no_aspm(void); >> bool pcie_aspm_support_enabled(void); >> bool pcie_aspm_enabled(struct pci_dev *pdev); >> +void pcie_encode_t_power_on(u16 t_power_on_us, u8 *scale, u8 *value); > This looks like it should go in drivers/pci/pci.h. I don't think it's > needed outside drivers/pci/. ack, I will fix in next patch. - Krishna Chaitanya. >> #else >> static inline int pci_disable_link_state(struct pci_dev *pdev, int state) >> { return 0; } >> @@ -1923,6 +1924,7 @@ static inline int pci_enable_link_state_locked(struct pci_dev *pdev, int state) >> static inline void pcie_no_aspm(void) { } >> static inline bool pcie_aspm_support_enabled(void) { return false; } >> static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; } >> +static inline void pcie_encode_t_power_on(u16 t_power_on_us, u8 *scale, u8 *value) { } >> #endif >> >> #ifdef CONFIG_HOTPLUG_PCI >> >> -- >> 2.34.1 >>