From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out30-130.freemail.mail.aliyun.com (out30-130.freemail.mail.aliyun.com [115.124.30.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 64B5734AB06 for ; Mon, 16 Mar 2026 06:25:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.130 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773642323; cv=none; b=N05RFU6JJlb7KsJrbSzTsq64ISXnLcA54CrBCFPGBu/x5G/nYNgJE5Xia2JPjky8Ekr3K3PTBJvmB3dNcE4hNpP1JLYKY/w9CN5W0tybwcqNV5It5z7YxfZDGuw+qI/AXXD+pGBVhohahfqLrfuzJH6d0FIz2zifa30mrSAwN38= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773642323; c=relaxed/simple; bh=PfjVTnH7wi/+SrOadWAe1Ja6cikLGcYp5swCsrARKHc=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=AOVfAHsMU1htL6IUadO1WUF0c5o3ar96YHytq2A0efRj+Ow58MJPWicvE/mGACUnN+WhyfSVw6gaowvw1BUqrj330iqZwsfF7kpTelWhfp201mH4drbp9SwhRG3oHPZv2JK7mowa6SEu3mteDlWck7JRX2hbuXmCfRhVVyKFz+0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=vHi2ydNR; arc=none smtp.client-ip=115.124.30.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="vHi2ydNR" DKIM-Signature:v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1773642319; h=Message-ID:Date:MIME-Version:Subject:To:From:Content-Type; bh=GHrVuzmWPg0Uih3557YZ5qAt41GrwBcJIT++eX/grpM=; b=vHi2ydNREc+4jny7D0w8SVH4+nWVdXbFS+UoN1NlkZfPAIcPw5Cc9iIHf955OAWnd4D9BNsGoSiuio+V48QxKn1rmfyqZWjzXSI+X9TV8P0QgNce6ZqncV85BrYBGVxGSU5Vm6z84Uk3gx40SnXmiHVxhAT0jHPHgytFhvIvV1U= X-Alimail-AntiSpam:AC=PASS;BC=-1|-1;BR=01201311R141e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=maildocker-contentspam033037033178;MF=baolin.wang@linux.alibaba.com;NM=1;PH=DS;RN=20;SR=0;TI=SMTPD_---0X..tuWa_1773642316; Received: from 30.74.144.148(mailfrom:baolin.wang@linux.alibaba.com fp:SMTPD_---0X..tuWa_1773642316 cluster:ay36) by smtp.aliyun-inc.com; Mon, 16 Mar 2026 14:25:17 +0800 Message-ID: Date: Mon, 16 Mar 2026 14:25:15 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 1/5] mm: rmap: support batched checks of the references for large folios To: "David Hildenbrand (Arm)" , Barry Song <21cnbao@gmail.com> Cc: akpm@linux-foundation.org, catalin.marinas@arm.com, will@kernel.org, lorenzo.stoakes@oracle.com, ryan.roberts@arm.com, Liam.Howlett@oracle.com, vbabka@suse.cz, rppt@kernel.org, surenb@google.com, mhocko@suse.com, riel@surriel.com, harry.yoo@oracle.com, jannh@google.com, willy@infradead.org, dev.jain@arm.com, linux-mm@kvack.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <12132694536834262062d1fb304f8f8a064b6750.1770645603.git.baolin.wang@linux.alibaba.com> <43831628-a00f-4292-9797-cb96a029bb00@kernel.org> From: Baolin Wang In-Reply-To: <43831628-a00f-4292-9797-cb96a029bb00@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 3/10/26 4:17 PM, David Hildenbrand (Arm) wrote: > On 3/10/26 02:37, Baolin Wang wrote: >> >> >> On 3/7/26 4:02 PM, Barry Song wrote: >>> On Sat, Mar 7, 2026 at 10:22 AM Baolin Wang >>> wrote: >>>> >>>> >>>> >>>> >>>> Thanks. >>>> >>>> >>>> Yes. In addition, this will involve many architectures’ implementations >>>> and their differing TLB flush mechanisms, so it’s difficult to make a >>>> reasonable per-architecture measurement. If any architecture has a more >>>> efficient flush method, I’d prefer to implement an architecture‑specific >>>> clear_flush_young_ptes(). >>> >>> Right! Since TLBI is usually quite expensive, I wonder if a generic >>> implementation for architectures lacking clear_flush_young_ptes() >>> might benefit from something like the below (just a very rough idea): >>> >>> int clear_flush_young_ptes(struct vm_area_struct *vma, >>>                  unsigned long addr, pte_t *ptep, unsigned int nr) >>> { >>>          unsigned long curr_addr = addr; >>>          int young = 0; >>> >>>          while (nr--) { >>>                  young |= ptep_test_and_clear_young(vma, curr_addr, >>> ptep); >>>                  ptep++; >>>                  curr_addr += PAGE_SIZE; >>>          } >>> >>>          if (young) >>>                  flush_tlb_range(vma, addr, curr_addr); >>>          return young; >>> } >> >> I understand your point. I’m concerned that I can’t test this patch on >> every architecture to validate the benefits. Anyway, let me try this on >> my X86 machine first. > > In any case, please make that a follow-up patch :) Sure. However, after investigating RISC‑V and x86, I found that ptep_clear_flush_young() does not flush the TLB on these architectures: int ptep_clear_flush_young(struct vm_area_struct *vma, unsigned long address, pte_t *ptep) { /* * On x86 CPUs, clearing the accessed bit without a TLB flush * doesn't cause data corruption. [ It could cause incorrect * page aging and the (mistaken) reclaim of hot pages, but the * chance of that should be relatively low. ] * * So as a performance optimization don't flush the TLB when * clearing the accessed bit, it will eventually be flushed by * a context switch or a VM operation anyway. [ In the rare * event of it not getting flushed for a long time the delay * shouldn't really matter because there's no real memory * pressure for swapout to react to. ] */ return ptep_test_and_clear_young(vma, address, ptep); } I don't have access to other architectures, so I think we can postpone this optimization unless someone is interested in optimizing the TLB flush.