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Mon, 10 Mar 2025 08:58:48 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 52A8wl9C023922 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Mar 2025 08:58:47 GMT Received: from [10.239.28.138] (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 10 Mar 2025 01:58:44 -0700 Message-ID: Date: Mon, 10 Mar 2025 16:58:42 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 0/2] phy: qcom: qmp-pcie: Add PCIe PHY no_csr reset support To: , , , , , , , , , , , , References: <20250226103600.1923047-1-quic_wenbyao@quicinc.com> Content-Language: en-US From: "Wenbin Yao (Consultant)" In-Reply-To: <20250226103600.1923047-1-quic_wenbyao@quicinc.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=WsDRMcfv c=1 sm=1 tr=0 ts=67cea9c8 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=VwQbUJbxAAAA:8 a=COk6AnOGAAAA:8 a=7YptvZ3fydEw2Y-QB6AA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: j-lWSNpmGh4X7HbiHVLoRMxg8XcSMW_8 X-Proofpoint-ORIG-GUID: j-lWSNpmGh4X7HbiHVLoRMxg8XcSMW_8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-10_03,2025-03-07_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 bulkscore=0 adultscore=0 impostorscore=0 phishscore=0 mlxscore=0 mlxlogscore=999 clxscore=1015 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2503100070 On 2/26/2025 6:35 PM, Wenbin Yao wrote: > The series aims to skip phy register programming and drive PCIe PHY with > register setting programmed in bootloader by simply toggling no_csr reset, > which once togglled, PHY hardware will be reset while PHY registers are > retained. > > First, determine whether PHY setting can be skipped by checking > QPHY_START_CTRL register and the existence of nocsr reset. If it is > programmed and no_csr reset is supported, do no_csr reset and skip BCR > reset which will reset entire PHY. > > This series also remove has_nocsr_reset flag in qmp_phy_cfg structure and > decide whether the PHY supports nocsr reset by checking the existence of > nocsr reset in device tree. > > The series are tested on X1E80100-QCP and HDK8550. > > The commit messages of this patchset have been modified based on comments > and suggestions. > > Changes in v5: > - Add a check whether the init sequences are exist if the PHY needs to be > initialized to Patch 2/2. > - Link to v4: https://lore.kernel.org/all/20250220102253.755116-1-quic_wenbyao@quicinc.com/ > > Changes in v4: > - Add Philipp's Reviewed-by tag to Patch 1/2. > - Use PHY instead of phy in comments in Patch 2/2. > - Use "if (qmp->nocsr_reset)" instead of "if (!qmp->nocsr_reset)" in > function qmp_pcie_exit for readability in Patch 2/2. > - Use goto statements in function qmp_pcie_power_on and qmp_pcie_power_off > for readability in Patch 2/2. > - Refine the comment of why not checking qmp->skip_init when reset PHY in > function qmp_pcie_power_off in Patch 2/2. > - Link to v3: https://lore.kernel.org/all/20250214104539.281846-1-quic_wenbyao@quicinc.com/ > > Changes in v3: > - Replace devm_reset_control_get_exclusive with > devm_reset_control_get_optional_exclusive when get phy_nocsr reset > control in Patch 1/2. > - Do not ignore -EINVAL when get phy_nocsr reset control in Patch 1/2. > - Replace phy_initialized with skip_init in struct qmp_pcie in Patch 2/2. > - Add a comment to why not check qmp->skip_init in function > qmp_pcie_power_off in Patch 2/2. > - Link to v2: https://lore.kernel.org/all/20250211094231.1813558-1-quic_wenbyao@quicinc.com/ > > Changes in v2: > - Add Abel's and Manivannan's Reviewed-by tag to Patch 1/2. > - Refine commit msg of Patch 2/2. > - Link to v1: https://lore.kernel.org/all/20250121094140.4006801-1-quic_wenbyao@quicinc.com/ > > Konrad Dybcio (1): > phy: qcom: pcie: Determine has_nocsr_reset dynamically > > Qiang Yu (1): > phy: qcom: qmp-pcie: Add PHY register retention support > > drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 86 +++++++++++++++++------- > 1 file changed, 63 insertions(+), 23 deletions(-) > > > base-commit: bcf2acd8f64b0a5783deeeb5fd70c6163ec5acd7 Hi, do you have any futher comments? -- With best wishes Wenbin