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[88.156.142.67]) by smtp.gmail.com with ESMTPSA id t27-20020ac24c1b000000b004a0589786ddsm430835lfq.69.2022.12.13.08.30.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 13 Dec 2022 08:30:11 -0800 (PST) Message-ID: Date: Tue, 13 Dec 2022 17:30:09 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.5.1 Subject: Re: [PATCH v2 04/13] arm64: dts: qcom: sc7180: Remove reg-names property from LLCC node Content-Language: en-US To: Manivannan Sadhasivam , andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, stable@vger.kernel.org References: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> <20221212123311.146261-5-manivannan.sadhasivam@linaro.org> From: Krzysztof Kozlowski In-Reply-To: <20221212123311.146261-5-manivannan.sadhasivam@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12/12/2022 13:33, Manivannan Sadhasivam wrote: > The LLCC block has several banks each with a different base address > and holes in between. So it is not a correct approach to cover these > banks with a single offset/size. Instead, the individual bank's base > address needs to be specified in devicetree with the exact size. > > On SC7180, there is only one LLCC bank available. So only change needed is > to remove the reg-names property from LLCC node to conform to the binding. > > The driver is expected to parse the reg field based on index to get the > addresses of each LLCC banks. > > Cc: # 5.6 Oh, no, there is no single bug here. Binding from v5.6+ (which cannot be changed) required/defined such reg-names. This is neither a bug nor possible to backport. > Fixes: c831fa299996 ("arm64: dts: qcom: sc7180: Add Last level cache controller node") Drop. > Reported-by: Parikshit Pareek > Signed-off-by: Manivannan Sadhasivam > --- > arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi > index f71cf21a8dd8..b0d524bbf051 100644 > --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi > @@ -2759,7 +2759,6 @@ dc_noc: interconnect@9160000 { > system-cache-controller@9200000 { > compatible = "qcom,sc7180-llcc"; > reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; > - reg-names = "llcc_base", "llcc_broadcast_base"; That's an ABI break... > interrupts = ; > }; > Best regards, Krzysztof