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Tue, 02 Jun 2026 07:19:52 -0700 (PDT) Received: from intellaptop.lan ([2607:fea8:fc01:88aa:f1de:f35:7935:804f]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-8cec1d7ebd4sm19076986d6.23.2026.06.02.07.19.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 07:19:51 -0700 (PDT) Message-ID: Subject: Re: [PATCH 01/28] KVM: TDX/VMX: rework EPT_VIOLATION_EXEC_FOR_RING3_LIN into PROT_MASK From: mlevitsk@redhat.com To: Paolo Bonzini , linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: d.riley@proxmox.com, jon@nutanix.com, Sean Christopherson Date: Tue, 02 Jun 2026 10:19:50 -0400 In-Reply-To: <20260505195226.563317-2-pbonzini@redhat.com> References: <20260505195226.563317-1-pbonzini@redhat.com> <20260505195226.563317-2-pbonzini@redhat.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.52.4 (3.52.4-2.fc40) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Tue, 2026-05-05 at 21:51 +0200, Paolo Bonzini wrote: > From: Jon Kohler >=20 > EPT exit qualification bit 6 is used when mode-based execute control > is enabled, and reflects user executable addresses. Rework name to > reflect the intention and add to EPT_VIOLATION_PROT_MASK, which allows > simplifying the return evaluation in > tdx_is_sept_violation_unexpected_pending a pinch. >=20 > Rework handling in __vmx_handle_ept_violation to unconditionally clear > EPT_VIOLATION_PROT_USER_EXEC until MBEC is implemented, as suggested by > Sean [1]. >=20 > Note: Intel SDM Table 29-7 defines bit 6 as: > =C2=A0 If the "mode-based execute control" VM-execution control is 0, the > =C2=A0 value of this bit is undefined. If that control is 1, this bit is = the > =C2=A0 logical-AND of bit 10 in the EPT paging-structure entries used to > =C2=A0 translate the guest-physical address of the access causing the EPT > =C2=A0 violation. In this case, it indicates whether the guest-physical > =C2=A0 address was executable for user-mode linear addresses. >=20 > [1] https://lore.kernel.org/all/aCJDzU1p_SFNRIJd@google.com/ >=20 > Suggested-by: Sean Christopherson > Signed-off-by: Jon Kohler > Message-ID: <20251223054806.1611168-2-jon@nutanix.com> > Tested-by: David Riley > Signed-off-by: Paolo Bonzini > --- > =C2=A0arch/x86/include/asm/vmx.h | 5 +++-- > =C2=A0arch/x86/kvm/vmx/common.h=C2=A0 | 9 +++++++-- > =C2=A0arch/x86/kvm/vmx/tdx.c=C2=A0=C2=A0=C2=A0=C2=A0 | 2 +- > =C2=A03 files changed, 11 insertions(+), 5 deletions(-) >=20 > diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h > index 37080382df54..b2291a766e3f 100644 > --- a/arch/x86/include/asm/vmx.h > +++ b/arch/x86/include/asm/vmx.h > @@ -608,10 +608,11 @@ enum vm_entry_failure_code { > =C2=A0#define EPT_VIOLATION_PROT_READ BIT(3) > =C2=A0#define EPT_VIOLATION_PROT_WRITE BIT(4) > =C2=A0#define EPT_VIOLATION_PROT_EXEC BIT(5) > -#define EPT_VIOLATION_EXEC_FOR_RING3_LIN BIT(6) > +#define EPT_VIOLATION_PROT_USER_EXEC BIT(6) > =C2=A0#define EPT_VIOLATION_PROT_MASK (EPT_VIOLATION_PROT_READ=C2=A0 | \ > =C2=A0 EPT_VIOLATION_PROT_WRITE | \ > - EPT_VIOLATION_PROT_EXEC) > + EPT_VIOLATION_PROT_EXEC=C2=A0 | \ > + EPT_VIOLATION_PROT_USER_EXEC) > =C2=A0#define EPT_VIOLATION_GVA_IS_VALID BIT(7) > =C2=A0#define EPT_VIOLATION_GVA_TRANSLATED BIT(8) > =C2=A0 > diff --git a/arch/x86/kvm/vmx/common.h b/arch/x86/kvm/vmx/common.h > index 412d0829d7a2..adf925500b9e 100644 > --- a/arch/x86/kvm/vmx/common.h > +++ b/arch/x86/kvm/vmx/common.h > @@ -94,8 +94,13 @@ static inline int __vmx_handle_ept_violation(struct kv= m_vcpu *vcpu, gpa_t gpa, > =C2=A0 /* Is it a fetch fault? */ > =C2=A0 error_code |=3D (exit_qualification & EPT_VIOLATION_ACC_INSTR) > =C2=A0 =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ? PFERR_FETCH_MASK : 0; > - /* ept page table entry is present? */ > - error_code |=3D (exit_qualification & EPT_VIOLATION_PROT_MASK) > + /* > + * ept page table entry is present? > + * note: unconditionally clear USER_EXEC until mode-based > + * execute control is implemented > + */ > + error_code |=3D (exit_qualification & > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (EPT_VIOLATION_PROT_MASK & ~EPT_VI= OLATION_PROT_USER_EXEC)) > =C2=A0 =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ? PFERR_PRESENT_MASK : 0; > =C2=A0 > =C2=A0 if (exit_qualification & EPT_VIOLATION_GVA_IS_VALID) > diff --git a/arch/x86/kvm/vmx/tdx.c b/arch/x86/kvm/vmx/tdx.c > index 1e47c194af53..89f9fe30435d 100644 > --- a/arch/x86/kvm/vmx/tdx.c > +++ b/arch/x86/kvm/vmx/tdx.c > @@ -1845,7 +1845,7 @@ static inline bool tdx_is_sept_violation_unexpected= _pending(struct kvm_vcpu *vcp > =C2=A0 if (eeq_type !=3D TDX_EXT_EXIT_QUAL_TYPE_PENDING_EPT_VIOLATION) > =C2=A0 return false; > =C2=A0 > - return !(eq & EPT_VIOLATION_PROT_MASK) && !(eq & EPT_VIOLATION_EXEC_FOR= _RING3_LIN); > + return !(eq & EPT_VIOLATION_PROT_MASK); > =C2=A0} > =C2=A0 > =C2=A0static int tdx_handle_ept_violation(struct kvm_vcpu *vcpu) Looks OK to me, Reviewed-by: Maxim Levitsky Best regards, Maxim Levitsky