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Tue, 14 Oct 2025 17:31:11 -0700 From: Nicolin Chen To: , CC: , , , , , , , Subject: [PATCH v2 7/7] iommufd/selftest: Add coverage for IOMMU_OPTION_SW_MSI_START/SIZE Date: Tue, 14 Oct 2025 17:29:39 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023D0:EE_|LV8PR12MB9232:EE_ X-MS-Office365-Filtering-Correlation-Id: 99617328-c7c6-4718-3588-08de0b822b0b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?AXn7Pxeo5S4v5RINR/tKIO3GCV73KI6mc+JsXNn4E3tw2IkwsIVFJGVnsEEf?= =?us-ascii?Q?o0VZn3qwsu00igjVP901xbJebfl/gRp2XgBmtJBlV/XADoh2feOzpS2unt9C?= =?us-ascii?Q?PjUcva+BEqN65tF2fACEQmjrkhYACs9YUOAsBgaTPDp62qI5QU+TUqocULVL?= =?us-ascii?Q?aw3nHEm/kgZJJvjS6bp0+5sDKEMgXEwdbqzeZXZVUZcJ/lln8f+dUheIGm0I?= =?us-ascii?Q?ZSoXPBlaw4kOAhnBSYdizkmf+l9YSpwbr7vsjeFiu9taF4hFljSXy5lw7wYd?= =?us-ascii?Q?dX+OG3Dofi/FVr2RhdhhqGbLo9t+fhWgaTNjLgXafHxP0ilI1RSu1cQqUs8D?= =?us-ascii?Q?GnXMI/eQyge+juTVkqgNK8199PBA1UeIuAyA/AENSt0o/bKDj0tOsDsRqGhU?= =?us-ascii?Q?UbV2F9o1wvyqNrdSuWLu5W3jtGoDfiDYe1OY8JGDIy1uc3ebKe93Mv3Yo6BB?= =?us-ascii?Q?VoXY9ujeSzKkXGhgQvrzMzCc9afpmnHIqSc/bLfkCPp9eRxORhQya3+/eYCB?= =?us-ascii?Q?icv+wX9buT+siRZ+brXcjGS0J3aenEA1hI6zLlQ9lYj+CkSeVHRz7gXAeMld?= =?us-ascii?Q?iOLmllYybUr1ktiShHOWTTCc++y/k3ufBZeXA0/AGNteaqac2HdYHgacHEv1?= =?us-ascii?Q?DdDJZhVL4bTF8hiv+Q8zwL57nWhCWXPb4gDU7UeHhXDPgoeYVp70lh5+rsKF?= =?us-ascii?Q?qZdBeqt6Kpl9nohLcpGm+/eg0VTW7Rbi5Pe/1/JLECaCLEr/0Vb1ICPrzF8x?= =?us-ascii?Q?/tTurIxMFhGMLcGU8iHfkMQQQssyR+HOYfj2AvgyMMosRy+lACEKZXmWpRge?= =?us-ascii?Q?tH+6ePCVpWd7saQMisSVURvworzEDQYpPXnSjE0sby3IQ2P4FRplF/O349kZ?= =?us-ascii?Q?efKCELlm8gudSNiQYnv5sFeJUepuitvYMCCMNMWIfikl7JAju20vhnn4lk9Y?= =?us-ascii?Q?4BHO4TMwFvDq/aMxkhebtTKJpP30p5MWtJZLjMIQARINUDW2h4i31ngIWZ3j?= =?us-ascii?Q?dhjLxJRkUdVl2u/JnAf+kDEzx5cYAjR140AsDF5pJtBAso6OKcUl7pQquFNe?= =?us-ascii?Q?7JAXnk0ndxu0f+HfxaYuXBP8CKYK/gK9k9na/Gzq2M1lznb+jlhC1LBNB7q/?= =?us-ascii?Q?UdXKpEczeUXbDOiVRzbPi6YoFwz4lMJ+HgxVxkcw33FU9DUBvlwg//w6TUby?= =?us-ascii?Q?rqdqjFLVZvONas40zF4+dIN3knAP786hHcVj2LYNllaOwVt/7LCCh7SIKHMx?= =?us-ascii?Q?mk85Dz8DT88pefIN17XOOy2UG9t7PONIwS+kUTSCCPv26DJZAwpq48OC58eR?= =?us-ascii?Q?O2FnA7KmFb3wJ6qrpG7W88JX3HCyfwX1edYtVz4rFMK9nbMSE7IVrR7fzhy/?= =?us-ascii?Q?eSWL675kItGz/niOTbLwbA1Z5GCYQ0KJ61MrcgfKdPg7IX0AarHtsrEBsei/?= =?us-ascii?Q?vOJ1W2sqxasA/CNmsFm7Z4xmunGsDfzvwU8gdgRLG4fnoTgi3BprUlu4EPSf?= =?us-ascii?Q?EC/rHEvmselUiuvHOA0PiWtK0BJIBx5iRj28EB/fGE7/pL9mQeVda5kpeMVT?= =?us-ascii?Q?oV10aCglqQsbfwRnP3U=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Oct 2025 00:31:22.8700 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 99617328-c7c6-4718-3588-08de0b822b0b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D0.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9232 Also add fail_nth coverage too. Signed-off-by: Nicolin Chen --- tools/testing/selftests/iommu/iommufd.c | 105 ++++++++++++++++++ .../selftests/iommu/iommufd_fail_nth.c | 21 ++++ 2 files changed, 126 insertions(+) diff --git a/tools/testing/selftests/iommu/iommufd.c b/tools/testing/selftests/iommu/iommufd.c index 3eebf5e3b974f..d67b1ac3e60a6 100644 --- a/tools/testing/selftests/iommu/iommufd.c +++ b/tools/testing/selftests/iommu/iommufd.c @@ -336,6 +336,111 @@ TEST_F(change_process, basic) ASSERT_EQ(child, waitpid(child, NULL, 0)); } +FIXTURE(iommufd_sw_msi) +{ + int fd; + uint32_t ioas_id; + uint32_t idev_id[2]; +}; + +FIXTURE_SETUP(iommufd_sw_msi) +{ + self->fd = open("/dev/iommu", O_RDWR); + ASSERT_NE(-1, self->fd); + + test_ioctl_ioas_alloc(&self->ioas_id); + test_cmd_mock_domain(self->ioas_id, NULL, NULL, &self->idev_id[0]); + test_cmd_mock_domain_flags(self->ioas_id, MOCK_FLAGS_DEVICE_NO_ATTACH, + NULL, NULL, &self->idev_id[1]); +} + +FIXTURE_TEARDOWN(iommufd_sw_msi) +{ + teardown_iommufd(self->fd, _metadata); +} + +TEST_F(iommufd_sw_msi, basic) +{ + struct iommu_option cmd = { + .size = sizeof(cmd), + .op = IOMMU_OPTION_OP_SET, + }; + + /* Negative case: object_id must be a device id */ + cmd.object_id = self->ioas_id; + cmd.option_id = IOMMU_OPTION_SW_MSI_START; + cmd.val64 = 0x70000000; + EXPECT_ERRNO(ENOENT, ioctl(self->fd, IOMMU_OPTION, &cmd)); + cmd.object_id = 0; + cmd.option_id = IOMMU_OPTION_SW_MSI_SIZE; + cmd.val64 = 2; + EXPECT_ERRNO(ENOENT, ioctl(self->fd, IOMMU_OPTION, &cmd)); + + /* Negative case: device must not be attached already */ + if (self->idev_id[0]) { + cmd.object_id = self->idev_id[0]; + cmd.option_id = IOMMU_OPTION_SW_MSI_START; + cmd.val64 = 0x70000000; + EXPECT_ERRNO(EBUSY, ioctl(self->fd, IOMMU_OPTION, &cmd)); + } + + /* Device isn't attached yet */ + if (self->idev_id[1]) { + /* Negative case: alignment failures */ + cmd.object_id = self->idev_id[1]; + cmd.option_id = IOMMU_OPTION_SW_MSI_START; + cmd.val64 = 0x7fffffff; + EXPECT_ERRNO(EINVAL, ioctl(self->fd, IOMMU_OPTION, &cmd)); + cmd.val64 = 0x7fffff00; + EXPECT_ERRNO(EINVAL, ioctl(self->fd, IOMMU_OPTION, &cmd)); + cmd.val64 = 0x7fff0000; + EXPECT_ERRNO(EINVAL, ioctl(self->fd, IOMMU_OPTION, &cmd)); + + /* Negative case: overlap against [0x80000000, 0x80ffffff] */ + cmd.option_id = IOMMU_OPTION_SW_MSI_START; + cmd.val64 = 0x80000000; + EXPECT_ERRNO(EADDRINUSE, ioctl(self->fd, IOMMU_OPTION, &cmd)); + cmd.val64 = 0x80400000; + EXPECT_ERRNO(EADDRINUSE, ioctl(self->fd, IOMMU_OPTION, &cmd)); + cmd.val64 = 0x80800000; + EXPECT_ERRNO(EADDRINUSE, ioctl(self->fd, IOMMU_OPTION, &cmd)); + cmd.val64 = 0x80c00000; + EXPECT_ERRNO(EADDRINUSE, ioctl(self->fd, IOMMU_OPTION, &cmd)); + /* Though an address that starts 1MB below will be okay ... */ + cmd.val64 = 0x7ff00000; + ASSERT_EQ(0, ioctl(self->fd, IOMMU_OPTION, &cmd)); + /* ... but not with a 2MB size */ + cmd.option_id = IOMMU_OPTION_SW_MSI_SIZE; + cmd.val64 = 2; + EXPECT_ERRNO(EADDRINUSE, ioctl(self->fd, IOMMU_OPTION, &cmd)); + + /* Negative case: overflows with the 2MB size */ + cmd.option_id = IOMMU_OPTION_SW_MSI_START; + cmd.val64 = UINT64_MAX - 1 * 1024 * 1024 + 1; + ASSERT_EQ(0, ioctl(self->fd, IOMMU_OPTION, &cmd)); + cmd.option_id = IOMMU_OPTION_SW_MSI_SIZE; + cmd.val64 = 2; + EXPECT_ERRNO(EOVERFLOW, ioctl(self->fd, IOMMU_OPTION, &cmd)); + + /* Set a safe 2MB window */ + cmd.option_id = IOMMU_OPTION_SW_MSI_START; + cmd.val64 = 0x70000000; + ASSERT_EQ(0, ioctl(self->fd, IOMMU_OPTION, &cmd)); + cmd.option_id = IOMMU_OPTION_SW_MSI_SIZE; + cmd.val64 = 2; + ASSERT_EQ(0, ioctl(self->fd, IOMMU_OPTION, &cmd)); + + /* Read them back to verify */ + cmd.op = IOMMU_OPTION_OP_GET; + cmd.option_id = IOMMU_OPTION_SW_MSI_START; + ASSERT_EQ(0, ioctl(self->fd, IOMMU_OPTION, &cmd)); + ASSERT_EQ(cmd.val64, 0x70000000); + cmd.option_id = IOMMU_OPTION_SW_MSI_SIZE; + ASSERT_EQ(0, ioctl(self->fd, IOMMU_OPTION, &cmd)); + ASSERT_EQ(cmd.val64, 2); + } +} + FIXTURE(iommufd_ioas) { int fd; diff --git a/tools/testing/selftests/iommu/iommufd_fail_nth.c b/tools/testing/selftests/iommu/iommufd_fail_nth.c index 45c14323a6183..19f23519b7914 100644 --- a/tools/testing/selftests/iommu/iommufd_fail_nth.c +++ b/tools/testing/selftests/iommu/iommufd_fail_nth.c @@ -621,6 +621,10 @@ TEST_FAIL_NTH(basic_fail_nth, access_pin_domain) /* device.c */ TEST_FAIL_NTH(basic_fail_nth, device) { + struct iommu_option cmd = { + .size = sizeof(cmd), + .op = IOMMU_OPTION_OP_SET, + }; struct iommu_hwpt_selftest data = { .iotlb = IOMMU_TEST_IOTLB_DEFAULT, }; @@ -632,6 +636,7 @@ TEST_FAIL_NTH(basic_fail_nth, device) uint32_t ioas_id; uint32_t ioas_id2; uint32_t idev_id; + uint32_t idev_id2; uint32_t hwpt_id; uint32_t viommu_id; uint32_t hw_queue_id; @@ -742,6 +747,22 @@ TEST_FAIL_NTH(basic_fail_nth, device) self->pasid = 0; + if (_test_cmd_mock_domain_flags(self->fd, ioas_id, + MOCK_FLAGS_DEVICE_NO_ATTACH, NULL, NULL, + &idev_id2)) + return -1; + + cmd.object_id = idev_id2; + cmd.option_id = IOMMU_OPTION_SW_MSI_START; + cmd.val64 = 0x70000000; + if (ioctl(self->fd, IOMMU_OPTION, &cmd)) + return -1; + + cmd.option_id = IOMMU_OPTION_SW_MSI_SIZE; + cmd.val64 = 2; + if (ioctl(self->fd, IOMMU_OPTION, &cmd)) + return -1; + return 0; } -- 2.43.0