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Fri, 18 Nov 2022 05:20:52 -0800 (PST) Received: from [192.168.31.208] ([194.29.137.22]) by smtp.gmail.com with ESMTPSA id z20-20020a196514000000b004b257fef958sm662505lfb.94.2022.11.18.05.20.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 18 Nov 2022 05:20:52 -0800 (PST) Message-ID: Date: Fri, 18 Nov 2022 14:20:50 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH 03/15] tty: serial: qcom-geni-serial: align #define values To: Bartosz Golaszewski , Andy Gross , Bjorn Andersson , Greg Kroah-Hartman , Jiri Slaby , Srinivas Kandagatla , Vinod Koul , Alex Elder Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-serial@vger.kernel.org, Bartosz Golaszewski References: <20221118122539.384993-1-brgl@bgdev.pl> <20221118122539.384993-4-brgl@bgdev.pl> From: Konrad Dybcio In-Reply-To: <20221118122539.384993-4-brgl@bgdev.pl> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 18/11/2022 13:25, Bartosz Golaszewski wrote: > From: Bartosz Golaszewski > > Keep the #define symbols aligned for better readability. > > Signed-off-by: Bartosz Golaszewski > --- Reviewed-by: Konrad Dybcio Konrad > drivers/tty/serial/qcom_geni_serial.c | 62 +++++++++++++-------------- > 1 file changed, 31 insertions(+), 31 deletions(-) > > diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c > index 7af5df6833c7..97ee7c074b79 100644 > --- a/drivers/tty/serial/qcom_geni_serial.c > +++ b/drivers/tty/serial/qcom_geni_serial.c > @@ -39,57 +39,57 @@ > #define SE_UART_MANUAL_RFR 0x2ac > > /* SE_UART_TRANS_CFG */ > -#define UART_TX_PAR_EN BIT(0) > -#define UART_CTS_MASK BIT(1) > +#define UART_TX_PAR_EN BIT(0) > +#define UART_CTS_MASK BIT(1) > > /* SE_UART_TX_STOP_BIT_LEN */ > -#define TX_STOP_BIT_LEN_1 0 > -#define TX_STOP_BIT_LEN_2 2 > +#define TX_STOP_BIT_LEN_1 0 > +#define TX_STOP_BIT_LEN_2 2 > > /* SE_UART_RX_TRANS_CFG */ > -#define UART_RX_PAR_EN BIT(3) > +#define UART_RX_PAR_EN BIT(3) > > /* SE_UART_RX_WORD_LEN */ > -#define RX_WORD_LEN_MASK GENMASK(9, 0) > +#define RX_WORD_LEN_MASK GENMASK(9, 0) > > /* SE_UART_RX_STALE_CNT */ > -#define RX_STALE_CNT GENMASK(23, 0) > +#define RX_STALE_CNT GENMASK(23, 0) > > /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */ > -#define PAR_CALC_EN BIT(0) > -#define PAR_EVEN 0x00 > -#define PAR_ODD 0x01 > -#define PAR_SPACE 0x10 > +#define PAR_CALC_EN BIT(0) > +#define PAR_EVEN 0x00 > +#define PAR_ODD 0x01 > +#define PAR_SPACE 0x10 > > /* SE_UART_MANUAL_RFR register fields */ > -#define UART_MANUAL_RFR_EN BIT(31) > -#define UART_RFR_NOT_READY BIT(1) > -#define UART_RFR_READY BIT(0) > +#define UART_MANUAL_RFR_EN BIT(31) > +#define UART_RFR_NOT_READY BIT(1) > +#define UART_RFR_READY BIT(0) > > /* UART M_CMD OP codes */ > -#define UART_START_TX 0x1 > +#define UART_START_TX 0x1 > /* UART S_CMD OP codes */ > -#define UART_START_READ 0x1 > - > -#define UART_OVERSAMPLING 32 > -#define STALE_TIMEOUT 16 > -#define DEFAULT_BITS_PER_CHAR 10 > -#define GENI_UART_CONS_PORTS 1 > -#define GENI_UART_PORTS 3 > -#define DEF_FIFO_DEPTH_WORDS 16 > -#define DEF_TX_WM 2 > -#define DEF_FIFO_WIDTH_BITS 32 > -#define UART_RX_WM 2 > +#define UART_START_READ 0x1 > + > +#define UART_OVERSAMPLING 32 > +#define STALE_TIMEOUT 16 > +#define DEFAULT_BITS_PER_CHAR 10 > +#define GENI_UART_CONS_PORTS 1 > +#define GENI_UART_PORTS 3 > +#define DEF_FIFO_DEPTH_WORDS 16 > +#define DEF_TX_WM 2 > +#define DEF_FIFO_WIDTH_BITS 32 > +#define UART_RX_WM 2 > > /* SE_UART_LOOPBACK_CFG */ > -#define RX_TX_SORTED BIT(0) > -#define CTS_RTS_SORTED BIT(1) > -#define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED) > +#define RX_TX_SORTED BIT(0) > +#define CTS_RTS_SORTED BIT(1) > +#define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED) > > /* UART pin swap value */ > -#define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0) > +#define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0) > #define IO_MACRO_IO0_SEL 0x3 > -#define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4) > +#define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4) > #define IO_MACRO_IO2_IO3_SWAP 0x4640 > > /* We always configure 4 bytes per FIFO word */