From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6EF233DD506 for ; Wed, 25 Mar 2026 14:36:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774449407; cv=none; b=IUgyVqEQED7QRc7S+0LjCAW1vaZmfLLiThDWklx4Cmzrz3icKWlxnNBBCmKidwRx8hqDYrRJmqtQ3ouzHas/6RkRw/vbqaOB/uU2scz7JLS7li3yBmtreoDUhbt6cHuNk9uNeUx+rZ+UoEM8ZYTWxY2JgIsiJOs/o1zfcNf4xhc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774449407; c=relaxed/simple; bh=1s/oLbJCdbJG+H5bcsLc7QVlHnEEasfd6M2und9S9aM=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=Zpac3yc2h2VarI5MXqWRKXGSteIJ11UHTrjMD/Z29t+99UTGtPOkLouikCqc3AD7jIJOT4hdSofaGd7tZof06rQIQMv+mU7lvUbvNA0n0R4QakG5YDhX6Fo/nNFShdiOYJBdmsKHCVoVYd1LNrcRswZSgWLpkbZ4Q9PlyVpkFRo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Ehl7K/4r; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Ehl7K/4r" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 29837C4CEF7; Wed, 25 Mar 2026 14:36:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1774449406; bh=1s/oLbJCdbJG+H5bcsLc7QVlHnEEasfd6M2und9S9aM=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=Ehl7K/4rE1asXxBnk+ljYExLi38p1QY5H3JQPyU3Dw1aVS7AlxcjALQupCiBIbhK7 1XwxolSPpD2kzFv8Ve62pYgU2ezvRA70PlVSHqhsrj57EqZf26UdWCt+ylLwstzzcj mLAxBQf0BwgyX85q+y4HrWi0HolMOoyrhmhIDebh3oULdo5uid4NYYcdGGJIbXYYq+ b8Mdq17b/vt86HPndC0RdwQ26TSEnaW36fYjUJZj6xPEotLJD7x0DHO6L1MHOpTSqB MaBWZPAmmlrmDBl1Wp3uz/Ww7A2eHC5s38FLk4pgAgHm3UsU6SvNS2cGdxjWInlyPr Ir+GgF58W4yQQ== Date: Wed, 25 Mar 2026 14:36:43 +0000 From: "Lorenzo Stoakes (Oracle)" To: "David Hildenbrand (Arm)" Cc: Baolin Wang , Barry Song <21cnbao@gmail.com>, akpm@linux-foundation.org, catalin.marinas@arm.com, will@kernel.org, lorenzo.stoakes@oracle.com, ryan.roberts@arm.com, Liam.Howlett@oracle.com, vbabka@suse.cz, rppt@kernel.org, surenb@google.com, mhocko@suse.com, riel@surriel.com, harry.yoo@oracle.com, jannh@google.com, willy@infradead.org, dev.jain@arm.com, linux-mm@kvack.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v6 1/5] mm: rmap: support batched checks of the references for large folios Message-ID: References: <12132694536834262062d1fb304f8f8a064b6750.1770645603.git.baolin.wang@linux.alibaba.com> <43831628-a00f-4292-9797-cb96a029bb00@kernel.org> <86f611cb-1292-44e4-b629-6503135d33ca@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <86f611cb-1292-44e4-b629-6503135d33ca@kernel.org> On Mon, Mar 16, 2026 at 03:15:18PM +0100, David Hildenbrand (Arm) wrote: > On 3/16/26 07:25, Baolin Wang wrote: > > > > > > On 3/10/26 4:17 PM, David Hildenbrand (Arm) wrote: > >> On 3/10/26 02:37, Baolin Wang wrote: > >>> > >>> > >>> > >>> I understand your point. I’m concerned that I can’t test this patch on > >>> every architecture to validate the benefits. Anyway, let me try this on > >>> my X86 machine first. > >> > >> In any case, please make that a follow-up patch :) > > > > Sure. However, after investigating RISC‑V and x86, I found that > > ptep_clear_flush_young() does not flush the TLB on these architectures: > > > > int ptep_clear_flush_young(struct vm_area_struct *vma, > >                unsigned long address, pte_t *ptep) > > { > >     /* > >      * On x86 CPUs, clearing the accessed bit without a TLB flush > >      * doesn't cause data corruption. [ It could cause incorrect > >      * page aging and the (mistaken) reclaim of hot pages, but the > >      * chance of that should be relatively low. ] > >      * > >      * So as a performance optimization don't flush the TLB when > >      * clearing the accessed bit, it will eventually be flushed by > >      * a context switch or a VM operation anyway. [ In the rare > >      * event of it not getting flushed for a long time the delay > >      * shouldn't really matter because there's no real memory > >      * pressure for swapout to react to. ] > >      */ > >     return ptep_test_and_clear_young(vma, address, ptep); > > } > > You'd probably want an arch helper then, that tells you whether > a flush_tlb_range() after ptep_test_and_clear_young() is required. > > Or some special flush_tlb_range() helper. > > I agree that it requires more work. Sorry unclear here - does the series need more work or does a follow up patch need more work? As this is in mm-stable afaict. Thanks, Lorenzo > > -- > Cheers, > > David