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Thu, 24 Apr 2025 04:58:20 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 53O4wJBr014408 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 24 Apr 2025 04:58:19 GMT Received: from [10.217.217.202] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 23 Apr 2025 21:58:16 -0700 Message-ID: Date: Thu, 24 Apr 2025 10:28:07 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3] arm64: dts: qcom: add initial support for qcom sa8255p-ride To: Dmitry Baryshkov CC: Deepti Jaggi , , , , , , , , , , References: <20250422231249.871995-1-quic_djaggi@quicinc.com> <0482cd6b-53ca-41eb-8721-a83ce8a7c733@quicinc.com> Content-Language: en-US From: Shazad Hussain In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: ATL_-RxtzVD2Wrmd9qf9FPAsNsXmgdp_ X-Authority-Analysis: v=2.4 cv=OY6YDgTY c=1 sm=1 tr=0 ts=6809c4ec cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=VwQbUJbxAAAA:8 a=COk6AnOGAAAA:8 a=CfkQHp0pE3PK7BQ2rswA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: ATL_-RxtzVD2Wrmd9qf9FPAsNsXmgdp_ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDI0MDAyOSBTYWx0ZWRfX8D1a3H9LED6N YM3kPb85jjivBng3geQfSLIjxzyVGAhqLdsRr2OHmi44mjHGKfYPdaaFecvYzzkWO9Pl3tLvEe2 C1qzlFsH+Jw7iHX3jEjppFP/ycKA1cp9mzDT5DwcACsy4Di91nooOJzFyOjalkY93Dl/bs8asHf 4Of2GuX+Zt8T4yaTopAAn6VbOamyj9TBxbDAp+Qk4ybknoFAlOV2v6cPYRUR8sF8Iwq9F1avtPe XWj+8kftEGG22jhkEKOqDI2OtCGxbvvxWHTPGw3K1aJ9mppSfG1El9wyn2unWj/m2A1v7Xj7TJr yl8e9LukRJVRL8+UdfYPhsvtyC7RBl85/7zr1AjpSazqK/a5/zbc/BcIjhgPUOszjXeb69KZHf9 bYOmg15ZgaVnzdXIFSRFMrDpaxNZQIe07l/wMweGmenf+aE1O0o5tkWWVIAIsD2IJwI7th81 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.680,FMLib:17.12.80.40 definitions=2025-04-24_01,2025-04-22_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 suspectscore=0 mlxscore=0 clxscore=1015 malwarescore=0 mlxlogscore=999 phishscore=0 priorityscore=1501 spamscore=0 adultscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504240029 On 4/23/2025 7:32 PM, Dmitry Baryshkov wrote: > On Wed, Apr 23, 2025 at 10:16:57AM +0530, Shazad Hussain wrote: >> >> >> On 4/23/2025 4:42 AM, Deepti Jaggi wrote: >>> From: Nikunj Kela >>> >>> This adds basic support for the Qualcomm sa8255p platform and the >>> reference board: sa8255p-ride. The dt files describe the basics of the >>> SoC and enable booting to shell with ramdisk. >>> >>> The Qualcomm automotive sa8255p SoC utilizes firmware to configure platform >>> resources such as clocks, interconnects, and TLMM. Device drivers request >>> these resources through the SCMI power and performance protocols. The SCMI >>> platform supports resource aggregation and handles parallel requests from >>> agents, with each driver having a dedicated SCMI channel for communication. >>> >>> Co-developed-by: Shazad Hussain >>> Signed-off-by: Shazad Hussain >>> Signed-off-by: Nikunj Kela >>> Signed-off-by: Deepti Jaggi >>> --- >>> This patch is dependent on [2] for booting to shell and DT bindings. >>> >>> Changes in v3: >>> Removed the patches from original series [1]. >>> Added arm,max-msg and arm,max-msg-size DT property in scmi nodes. >>> Changed max-rx-timeout-ms to arm,max-rx-timeout-ms in scmi nodes. >>> Updated commit text. >>> Reordered range property for qupv3_id_0, qupv3_id_1 and qupv3_id_3 nodes. >>> Reordered vendor property(#qcom,sensors) for tsens* nodes. >>> Changed cache labels to lower case. >>> Removed unused i2c,spi and tlmm nodes. >>> Updated reserved memory nodes. >>> >>> Changes in v2: >>> Removed scmichannels label and alias >>> Modified scmi node name to conform to schema >>> Moved status property to be the last one in scmi instances >>> Changed to lower case for cpu labels >>> Added fallback compatible for tlmm node >>> >>> [1]: https://lore.kernel.org/all/20240903220240.2594102-1-quic_nkela@quicinc.com/ >>> [2]: https://lore.kernel.org/all/20250418151235.27787-1-quic_ptalari@quicinc.com/ >>> --- >>> arch/arm64/boot/dts/qcom/Makefile | 1 + >>> arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi | 80 + >>> arch/arm64/boot/dts/qcom/sa8255p-ride.dts | 94 + >>> arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi | 2440 +++++++++++++++++++ >>> arch/arm64/boot/dts/qcom/sa8255p.dtsi | 2075 ++++++++++++++++ >>> 5 files changed, 4690 insertions(+) >>> create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi >>> create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-ride.dts >>> create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi >>> create mode 100644 arch/arm64/boot/dts/qcom/sa8255p.dtsi >>> >>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile >>> index adb4d026bcc4..7437e51e5849 100644 >>> --- a/arch/arm64/boot/dts/qcom/Makefile >>> +++ b/arch/arm64/boot/dts/qcom/Makefile >>> @@ -134,6 +134,7 @@ qrb5165-rb5-vision-mezzanine-dtbs := qrb5165-rb5.dtb qrb5165-rb5-vision-mezzanin >>> dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5-vision-mezzanine.dtb >>> dtb-$(CONFIG_ARCH_QCOM) += qru1000-idp.dtb >>> dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb >>> +dtb-$(CONFIG_ARCH_QCOM) += sa8255p-ride.dtb >>> dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb >>> dtb-$(CONFIG_ARCH_QCOM) += sa8540p-ride.dtb >>> dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride.dtb >>> diff --git a/arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi b/arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi >>> new file mode 100644 >>> index 000000000000..b00c2b05cef7 >>> --- /dev/null >>> +++ b/arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi >>> @@ -0,0 +1,80 @@ >>> +// SPDX-License-Identifier: BSD-3-Clause >>> +/* >>> + * Copyright (c) 2024-2025, Qualcomm Innovation Center, Inc. All rights reserved. >>> + */ >>> + >>> +/ { >>> + thermal-zones { >>> + pmm8654au_0_thermal: pm8255-0-thermal { >>> + polling-delay-passive = <100>; >>> + >>> + trips { >>> + trip0 { >>> + temperature = <105000>; >>> + hysteresis = <0>; >>> + type = "passive"; >>> + }; >>> + >>> + trip1 { >>> + temperature = <125000>; >>> + hysteresis = <0>; >>> + type = "critical"; >>> + }; >>> + }; >>> + }; >>> + >>> + pmm8654au_1_thermal: pm8255-1-thermal { >>> + polling-delay-passive = <100>; >>> + >>> + trips { >>> + trip0 { >>> + temperature = <105000>; >>> + hysteresis = <0>; >>> + type = "passive"; >>> + }; >>> + >>> + trip1 { >>> + temperature = <125000>; >>> + hysteresis = <0>; >>> + type = "critical"; >>> + }; >>> + }; >>> + }; >>> + >>> + pmm8654au_2_thermal: pm8255-2-thermal { >>> + polling-delay-passive = <100>; >>> + >>> + trips { >>> + trip0 { >>> + temperature = <105000>; >>> + hysteresis = <0>; >>> + type = "passive"; >>> + }; >>> + >>> + trip1 { >>> + temperature = <125000>; >>> + hysteresis = <0>; >>> + type = "critical"; >>> + }; >>> + }; >>> + }; >>> + >>> + pmm8654au_3_thermal: pm8255-3-thermal { >>> + polling-delay-passive = <100>; >>> + >>> + trips { >>> + trip0 { >>> + temperature = <105000>; >>> + hysteresis = <0>; >>> + type = "passive"; >>> + }; >>> + >>> + trip1 { >>> + temperature = <125000>; >>> + hysteresis = <0>; >>> + type = "critical"; >>> + }; >>> + }; >>> + }; >>> + }; >>> +}; >> >> PMIC is handled by firmware on this SoC and in my openion we do not need >> to have a dedicated sa8255p-pmics.dtsi only to have thermal zones nodes. >> Can we keep these pmic thermal zones to sa8255p.dtsi with other thermal >> zones nodes ? > > For the PMIC? No, they are not a part of the SoC. Thanks Dmitry for the clarification ! -Shazad >