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([2001:b07:5d29:f42d:5c69:6d03:309e:bc47]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a4f0097205sm8774995f8f.79.2025.05.31.11.01.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 May 2025 11:01:20 -0700 (PDT) Message-ID: Subject: Re: [PATCH 17/28] KVM: SVM: Manually recalc all MSR intercepts on userspace MSR filter change From: Francesco Lavra To: seanjc@google.com Cc: bp@alien8.de, chao.gao@intel.com, dapeng1.mi@linux.intel.com, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, pbonzini@redhat.com, xin@zytor.com Date: Sat, 31 May 2025 20:01:18 +0200 In-Reply-To: <20250529234013.3826933-18-seanjc@google.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.46.4-2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On 2025-05-29 at 23:40, Sean Christopherson wrote: > @@ -81,70 +79,6 @@ static uint64_t osvw_len =3D 4, osvw_status; > =20 > static DEFINE_PER_CPU(u64, current_tsc_ratio); > =20 > -static const u32 direct_access_msrs[] =3D { > - MSR_STAR, > - MSR_IA32_SYSENTER_CS, > - MSR_IA32_SYSENTER_EIP, > - MSR_IA32_SYSENTER_ESP, > -#ifdef CONFIG_X86_64 > - MSR_GS_BASE, > - MSR_FS_BASE, > - MSR_KERNEL_GS_BASE, > - MSR_LSTAR, > - MSR_CSTAR, > - MSR_SYSCALL_MASK, > -#endif > - MSR_IA32_SPEC_CTRL, > - MSR_IA32_PRED_CMD, > - MSR_IA32_FLUSH_CMD, > - MSR_IA32_DEBUGCTLMSR, > - MSR_IA32_LASTBRANCHFROMIP, > - MSR_IA32_LASTBRANCHTOIP, > - MSR_IA32_LASTINTFROMIP, > - MSR_IA32_LASTINTTOIP, > - MSR_IA32_XSS, > - MSR_EFER, > - MSR_IA32_CR_PAT, > - MSR_AMD64_SEV_ES_GHCB, > - MSR_TSC_AUX, > - X2APIC_MSR(APIC_ID), > - X2APIC_MSR(APIC_LVR), > - X2APIC_MSR(APIC_TASKPRI), > - X2APIC_MSR(APIC_ARBPRI), > - X2APIC_MSR(APIC_PROCPRI), > - X2APIC_MSR(APIC_EOI), > - X2APIC_MSR(APIC_RRR), > - X2APIC_MSR(APIC_LDR), > - X2APIC_MSR(APIC_DFR), > - X2APIC_MSR(APIC_SPIV), > - X2APIC_MSR(APIC_ISR), > - X2APIC_MSR(APIC_TMR), > - X2APIC_MSR(APIC_IRR), > - X2APIC_MSR(APIC_ESR), > - X2APIC_MSR(APIC_ICR), > - X2APIC_MSR(APIC_ICR2), > - > - /* > - * Note: > - * AMD does not virtualize APIC TSC-deadline timer mode, but it > is > - * emulated by KVM. When setting APIC LVTT (0x832) register bit > 18, > - * the AVIC hardware would generate GP fault. Therefore, always > - * intercept the MSR 0x832, and do not setup direct_access_msr. > - */ > - X2APIC_MSR(APIC_LVTTHMR), > - X2APIC_MSR(APIC_LVTPC), > - X2APIC_MSR(APIC_LVT0), > - X2APIC_MSR(APIC_LVT1), > - X2APIC_MSR(APIC_LVTERR), > - X2APIC_MSR(APIC_TMICT), > - X2APIC_MSR(APIC_TMCCT), > - X2APIC_MSR(APIC_TDCR), > -}; > - > -static_assert(ARRAY_SIZE(direct_access_msrs) =3D=3D > - MAX_DIRECT_ACCESS_MSRS - 6 * !IS_ENABLED(CONFIG_X86_64)); > -#undef MAX_DIRECT_ACCESS_MSRS The MAX_DIRECT_ACCESS_MSRS define should now be removed from arch/x86/kvm/svm/svm.harch/x86/kvm/svm/svm.h, since it's no longer used.